I was reading Wikipedia about the von Neumann bottleneck.

Surely there is some simple answer to this. Why can we not read and write to the same address at the same time? We can if the addresses are different.

  • $\begingroup$ I don't think that even if this was possible it helped to solve the said bottleneck. The reason this bottleneck exists is because of the model we use for it is all but serial. So you are bound to look at program/data one bit at a time, but most of the time you need to load more than one bit to do any work. Thus you load-work-load-work etc. The hardware comes in as a factor in that it's slower at loading than it is at doing the actual work. $\endgroup$
    – wvxvw
    Oct 7 '15 at 21:45
  • $\begingroup$ i always thought it was because simultaneous read/write leads to logical inconsistencies $\endgroup$
    – JMP
    Oct 7 '15 at 21:53
  • $\begingroup$ To be completely honest, I'm not even sure how is it related. I mean, there's no way to have simultaneous read/write inside von Neumann computer to begin with (actually there's nothing simultaneous in it at all). It's kind of like talking about third dimension in planimetry. This problem might surface if you try an approach different from von Neumann architecture, but does it have to? - I don't know. $\endgroup$
    – wvxvw
    Oct 7 '15 at 22:01
  • $\begingroup$ the bottleneck is caused by the vN axiom that there must be a finite time gap between RW operations $\endgroup$
    – JMP
    Oct 7 '15 at 22:02
  • $\begingroup$ As a special case of the whole thing being serial, yes. But, the difference is that the problem happens in the framework which is consistent with this axiom. You seem to think that relaxing this requirement will change the framework in the way that the problem will go away, and I'm doubting that it will. $\endgroup$
    – wvxvw
    Oct 7 '15 at 22:07

In other models (a distributed architecture, for example, with several processors) you can often do concurrent reads, where two or more processors are able to read a word from memory simultaneously. The problem with concurrent writes is more complicated since you have the possibility of a race condition: if one processor wants to write 31 to a memory location and at the same time another processor wants to write 0 to that location, the behavior of the system might not be predictable so running a program twice might result in two different results. Dealing with this problem can be tricky, as you might imagine. That's not to say it can't be handled, only that it's more complicated.

  • $\begingroup$ Since von Neumann is an abstract model, why is it a problem there? It seems easy to define semantics that allow this. $\endgroup$
    – Raphael
    Oct 7 '15 at 18:45
  • $\begingroup$ you can often do concurrent reads, where two or more processors are able to read a word from memory simultaneously: are we actually reading/writing from/to cached copies at different places or really from/to a physical register or a memory location? $\endgroup$
    – hengxin
    Oct 8 '15 at 8:24

In my understanding, reading and writing to the same address "at the same time" (or called "simultaneously") in your post means that the read and the write "overlaps" with each other: every operation takes time, no matter how short it is.

The "overlapping" can be interpreted in different levels. At a high level, any two concurrent operations (i.e., no one ends before the other one starts) in a multiprocessor computer can be regarded "overlapping" with each other. (Also see the answer by @Rick Decker)

You are probably more interested in the case that "simultaneous" read & write happen on a physical level. If so, dual-port RAM may be relevant.

Quote from the "dual-port RAM" document:

The dual-port configuration has two separate blocks (block A and block B) and corresponding clocks (CLKA and CLKB). This allows the user to perform both read and write operations on both blocks A and B. However, when performing simultaneous operations there may be data collisions and undesired data may be obtained at the output.

Note: The information about "dual-port RAM" is from a comment on a question about "safe registers" at cs.theory.

  • $\begingroup$ nothing personal, this answer is fine - i am looking at the parallel version where we can RW simultaneously AS LONG AS THE ADRESSES ARE DIFFERENT $\endgroup$
    – JMP
    Oct 8 '15 at 10:31

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