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Is word size, the size of a memory location? the size of the data bus? or the cpu register size?

Suppose you have a computer,

memory address #0 has byte AB memory address #1 has byte F3 memory address #2 has byte EA So each memory address stores one byte.

And you have a data bus that can pick up 4 contiguous memory locations, bytes, at a time. So I suppose if the CPU wanted address 0, then it'd pick up address #0,#1,#2,#3 And if the CPU wanted address 1, then it'd pick up #1,#2#,3#,#4

And Case A, say the CPU register size is 64bit. (would that require two fetches? i'm not sure if that'd work). So alternatively, Case B, Let's say the CPU register size is 32bit

What is the word size? Is it the data bus size, the memory location size, or the cpu register size?

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  • $\begingroup$ Self-promotion: While it does not answer the question completely, this brief list of memory granule terms might be of interest. (Terminology can be confusing, e.g., Motorola called the 68000 a 16-bit processor despite having 32-bit address and data registers.) $\endgroup$ – Paul A. Clayton Oct 22 '15 at 2:09
  • $\begingroup$ @PaulA.Clayton 32bit processors based on x86(16bit), what's their word size? surely 32bit? A 64bit processor often called x86_64 is surely not 16bit word size for being based on x86 which had 16bit word size. Also your glossary doesn't define granule though I get that it's a piece of memory. $\endgroup$ – barlop Oct 22 '15 at 2:16
  • $\begingroup$ x86 uses "word" to mean 16-bit chunks. Effectively the term is not used in an entirely consistent manner, in part because of desire for compatibility (similar problems have occurred in C with int and long, where one can have il32p64 and i32lp64 on a 64-bit architecture even though 64-bits is the "natural" size int). $\endgroup$ – Paul A. Clayton Oct 22 '15 at 3:23
  • $\begingroup$ related- stackoverflow.com/questions/7750140/… $\endgroup$ – barlop Jan 18 '16 at 23:46
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This is one of those terms that can mean different things depending upon who you ask and the context in which it is asked.

Usually a processor's word size is defined as the largest size integer which it can operate on with a single arithmetic instruction. For example, 64 bit computer can add or subtract 64 bits with a single instruction. But that same computer may be able to operate on bytes, 16 bit words, and 32 bit longwords.

Don't equate the memory path with the computer's word size. Often data is moved into and out of cache in a fixed size block that is a multiple of the computer's word size. A 64 bit CPU has 8, 8 bit bytes per word but might use a 64 byte cache line and move data into and out of memory in cache block chunks, even if the CPU is only accessing 1 byte of the cache block. OR conversely, the data path to memory could be smaller, as the case with the old 8088 CPU. It used 16 bit CPU registers and did 16 bit arithmetic, but had an 8 bit data bus. It had to do 2 memory transfers to load or store a register.

And then there are fixed definitions for a word size, for example...

DEC had a problem with just saying WORD especially on VAX architecture, mostly because the company had built so many different computers with different natural word sizes (9, 18, 36, 12, 16, 32 and 64 that I can think of) and the VAX was capable of working with a large variety of data sizes. So they decided to define terms like WORD to have more definite meanings.
Byte = 8 bits, Word = 16 bits, Longword = 32 bits, Quadword = 64 bits, Octaword = 128 bits

This took much of the confusion out of discussions when a processor was capable of handling multiple different data sizes.


edit - I didn't really address this part of the question: "And you have a data bus that can pick up 4 contiguous memory locations, bytes, at a time. So I suppose if the CPU wanted address 0, then it'd pick up address #0,#1,#2,#3 And if the CPU wanted address 1, then it'd pick up #1,#2#,3#,#4"

Not usually.
IF a 64 bit computer is capable of addressing Longwords on a byte boundary, normally the system would load the cache block containing the address 0 from memory into cache. Often that will be on a multiple word cache size. So in the example I gave with a 64 byte cache line, the hardware would move the first 64 bytes into cache as a chunk. The CPU would then access the bytes from cache as you describe (well sort of, it may have to shift bytes to get them loaded correctly). If the longword you attempted to load spanned 2 cache blocks, the hardware would have to load 2 cache blocks (128 bytes) to access the 4 you were interested in. Or in the example you gave with a 32 bit data bus, it would have to load 64 bits (2 lines) to get the 32 that you want. If possible, it's best to align data on its natural boundary to avoid this and other data manipulations required to deal with unaligned data.

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  • $\begingroup$ You write "64 bit computer" <-- sounds a bit circular. 'cos which of these are 64bit. A)The CPU register B)data bus C)individual memory location D)address bus.. I know a 64bit computer has a 64bit CPU register , I don't know how big the data bus is. I know the individual memory locations are 1 byte. And I know the address bus is 64bit. But to illustrate it's better to give an example of a machine where theese are all different sizes, and then say what the word size is $\endgroup$ – barlop Oct 21 '15 at 19:56
  • $\begingroup$ And if we pretend for now, for simplicity, that processors have registes all same size then A)If a computer had 8 bit registers and a 16 bit address bus, is word size 8 bit or 16bit? B)If a computer had 16 bit registers and an 8 bit data bus, is word size 8 bit or 16 bit? $\endgroup$ – barlop Oct 21 '15 at 19:57
  • $\begingroup$ Yes I did use a bit of circular definition.... 8*) When I said 64 bit computer, I did mean a 64 bit ALU. And for your 8 bit alu with 16 bit address bus (sound like an 8080?) the word size is usually considered 8 bits though the 8080 could perform a limited number of instructions 16 bits at a time. $\endgroup$ – Brian Hibbert Oct 21 '15 at 20:17
  • $\begingroup$ What about A)8 bit registers and a 16 bit data bus? and B)16 bit registre and 8 bit data bus? $\endgroup$ – barlop Oct 21 '15 at 20:18
  • $\begingroup$ Again, usually when the term "word" is used, it's the largest data size that can be operated on in a single instruction. The data bus address size is a separate issue. a) Using a 16 bit address space and an 8 bit data path requires an addressing scheme that typically manipulates address register(s) loaded in 2 steps, and then can be used to access data at the address possibly with an auto increment of that register like the 8080 did it. B) Is the 8088 architecture. The hardware did 2 memory transfers for each register load, but it was mostly hidden from the programmer. $\endgroup$ – Brian Hibbert Oct 21 '15 at 20:30
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This is just an answer where I present things in my own words as I understand them.

Of the different factors - Address bus size, External Data bus size, size of memory location, size of cpu register.. Internal data bus size. Where any of those count, the only thing that counts is size of CPU register.

And regarding CPU registers.. you may get some specialised ones.. but it's the size of general purpose CPU registers. Word size being, the largest unit , or the unit, that an instruction can work/ works, on. So the size of a memory location is irrelevant, as multiple ones can be collected at a time, and the data bus size is irrelevant as multiple trips can be made back and forth, it doesn't affect word size. It's just the general purpose CPU registers that count.

That's one definition of word size.

Another definition is the case of DEC who made different computers with different word sizes and defined their terms word, and also longword and others. as set numbers of bits e.g word 16 bit.

And another definition, is for "compatibility"(assembly language?)see, an earlier parent architecture had a word size of e.g. 16bit and child architectures are said to have that word size. This is apparently the case with x86 processors.

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