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I have two opposing ideas. I think that all the instructions in a RISC take the same time what makes me believe RISC is associated with synchronous.

At the same time i think that CISC should be synchronous and RISC should be asynchronous.

Can you tell me if RISC is associated with asynchronous and CISC is associated with synchronous? Why?

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    $\begingroup$ Can't answer this question if you don't specify which "synchronous/asynchronous" concept it is about (these are broad terms). Please narrow the definition. $\endgroup$ – Yves Daoust Oct 21 '15 at 6:44
  • $\begingroup$ @YvesDaoust it's clock synchronous $\endgroup$ – DDDD Oct 21 '15 at 13:10
  • $\begingroup$ Then RISC/CISC really have nothing to do with that, but with general processor architecture and instruction set structure. $\endgroup$ – Yves Daoust Oct 21 '15 at 13:44
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I think that all the instructions in a RISC take the same time what makes me believe RISC is associated with synchronous.

It's not true that all instructions in a RISC CPU take the same time. Even in the classic RISC pipeline, the pipeline will stall in some circumstances. Pipeline interlocks and control hazards are the ones that Hennessy and Patterson go into some detail about, but they also mentioned data cache misses.

Even if you ignore those complications, it's unrealistic to design a general-purpose CPU where every instruction takes the same time these days. Programmers want floating point, and SIMD operations, and so on.

Can you tell me if RISC is associated with asynchronous and CISC is associated with synchronous?

On, that's easy: They're not.

Truly asynchronous CPUs are rare, for a few reasons. One of them is that you can't (currently) prototype asynchronous logic on a FPGA, and it's much harder to express in Verilog or VHDL than synchronous logic.

Having said that, it is easier to implement a RISC pipeline in asynchronous logic than a CISC pipeline (e.g. Sproull's Counterflow Pipeline). However, event his is a bit misleading because the boundary between RISC and CISC is quite fuzzy these days. Most modern CISC CPUs use RISC cores internally, and dynamically translate the CISC instruction stream into RISC code. The main reason for this is that the same features which make RISC attractive (e.g. fixed-size instructions which can be buffered) are also the ones which make superscalar execution work.

So to the extent that asynchronous logic works, modern CISC CPUs can benefit almost as much as RISC CPUs can.

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  • $\begingroup$ I am taking a first aprouch to computer science in a subject about embedded systems, so i don't know some concepts. In a teacher question he asks to stablish the nexus between CISC/RISC and clock synchronicity/asynchronicity of data transfer. What should i have answered? $\endgroup$ – DDDD Oct 21 '15 at 13:31
  • $\begingroup$ I'd have to see the exact question, but the two questions seem only tangentially related to me. $\endgroup$ – Pseudonym Oct 22 '15 at 1:34
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A purely asynchronous CPU would not need a clock, so just off that point alone it is clear that RISC and CISC are both synchronous as both have their operations granulated into clock bins.However, both RISC and CISC processors can have asynchronous logic blocks nestled between clocked components to achieve particular logic functions.

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