# How is clock syncing implemented?

I'm looking for an explanation or reference on the implementation of computer clock. To keep the question at the level of logical abstractions: say, we put together some combinational and sequential logic from basic gates. The role of the clock (an oscillator of some sort, but that's going into more detail than needed for my abstraction) is to synchronise the unorderly chorus of inputs and outputs passing through the gates. Exactly how does the clock synchronize the signals?

To render things more concrete... Take a two-way NAND gate. Say, I set the two inputs (U1) to high signal, and obtain (after some inherent delay) a stable low signal at the other end (U2). Now, to add basic sequential logic to this inverter, let's add a Data Flip-Flop (DFF). The effect is that we can be certain that the Q end of the DFF will broadcast the low signal "definitively" at the start of the next clock cycle. What happens within the cycle is not to be trusted. The clock period is set such that the other circuitry (NAND gate in my case) has the time to stabilize during the cycle. This is the contract. But how is it achieved?

The metaphor in my mind is that the clock acts as a sluice. But the comparison is misleading, in that the signal entering and exiting the DFF is not truncated at any point. We could physically measure the signal within the tick-tock cycle of the clock at the Q end of the DFF. Another high-flown metaphor would be the warm-up motions of an orchestra before the rehearsal gradually transforming into an attuned performance, with the conductor setting the beat.

How is the proper signal (attuned to the clock's oscillations) distinguished from the noise propagating through gate circuitry at all times? I realize, there may be missing parts in my picture, so that question should be framed in constructive terms: How can one implement this basic circuit to allow the logic to distinguish between signal and noise? Edit: Judging by responses to this question, my original question must be poorly phrased. I understand the reasons behind the choice of frequency for the system clock to ensure the circuit is stable on the tick of the clock. The responses from @Ran G. and @slebetman emphasize the "contractual" side of things. My question is really about why the contract holds. In retrospect, what I was getting at is the trivial fact that measuring instruments (system clock) must be selected based on the degree of precision required -- in a typical case discussed here, for our human sluggish attention span.

To illustrate, here's a graph of the clock pulse against data-in and Qa output for a DFF. Say, in the 2nd clock cycle, Captain Marvel sends a pulse on the data-in line and -- oblivious to the clock period -- expects to read it off immediately (mid-phase). With his lightning speed, there's no way he can make sense of the output of this circuit because the clock cycle is geological time to him. Billy Watson, on the other hand, can read it just fine. Neither Captain M. nor Billy W. is synchronized with the system clock. Not in the sense that the gate circuitry is. But for Billy's experience of time, the clock's time scale is sufficiently precise.

You have a good understanding of clocking mechanism and how flip-flops (registers really, can be implemented using any clocked memory, not just flip-flops) are used to get a "final" reading after all propagation of signals have stabilized. But your question:

The clock period is set such that the other circuitry (NAND gate in my case) has the time to stabilize during the cycle. This is the contract. But how is it achieved?

Perhaps is overthinking it. It is never achieved. Rather, it is specified. Basically you read the user manual (or in engineering it's usually the data sheet). If the user manual says the maximum clock is 100MHz then you don't supply it with a 200MHz clock.

That's the basic mechanism of how it's "achieved".

So, I can already see the next question forming: How do the designers know to specify 100MHz? It can't be arbitrary can it?

The basic way it's done is to calculate the timing of all propagation. Say you have this circuit:

output = A && (B || C || (D && E))


Lets say all OR and AND gates have the same propagation time: 1ns. Lets also re-arrange the circuit above to make things clearer:

            A
/
output = &&    B     D
\  /     /
||    &&
\  /  \
||    E
\
C


So, in the above circuit, the longest path to output is the input from D and E. It passes through four gates (assuming gates can only have two inputs, you can do three levels if you use a three input OR gate). Since each gate takes 1ns to stabilize, the circuit above can be sampled at a rate of every 4ns or 250MHz.

The calculations above are simplified of course. It assumes wires have zero propagation time and also assume that inputs are simultaneous. Real-world CAD software can calculate propagation time of wires/traces and can even lengthen traces if necessary to ensure signals arrive at the same time. As for the simultaneity of the inputs, that's the user's (the engineer using your component) problem. If the outputs from his circuit take time to stabilize before going in to your circuit he has to take that into account and use a slower clock to allow the signals to stabilize.

There is also the dirty way to do the above calculations: overclocking. You keep increasing the clock frequency to your system until it fails then back off a bit until it works again then back off a bit more to allow for some overhead.

There's also a third question and it is part of the assumption of almost every digital designer: When we clock, how are we SURE the inputs have stabilized? We've only accounted for the outputs of our gates, not the inputs to them?

The answer is that inputs to our circuit comes form another circuit in our system. They synchronize by using the same clock. Since they were clocked at the end of the previous clock cycle, we assume they're stable at the beginning of this clock cycle. Which is why we only consider the propagation of the gates as the limiting factor for the stability of signals.

All non-internal signals or all signals that don't share our clock must be sampled. That's part of the reason that external signals can never be as fast as our internal clock - it's to allow for them to be stable in a register somewhere before signaling to the internal circuits that they're ready to enter our system.

So in general, in terms of signal stability, we assume noise only exists between clock pulses and all the signals in our entire system should stabilize before the next clock pulse. That effectively defines our maximum clock rate.

I feel there are multiple questions in your post. I will attempt to answer the first -

"...The clock period is set such that the other circuitry (NAND gate in my case) has the time to stabilize during the cycle. This is the contract. But how is it achieved?

Shown below is a transistor level circuit of the D flip-flop shown in the picture in your post. If you replace your D-ff schematic with the above picture, you can see how the signal propagates from the D input to the Q output.

How can one implement this basic circuit to allow the logic to distinguish between signal and noise?

Logic does not distinguish signal from noise. Noise is a signal. It is an (usually) unwanted signal, but a signal all the same. It is the job of the designer to ensure that noise from various sources does not pollute the actual signal so much that it results in an incorrect reading at the Q output.

Circuits have some amount of noise immunity. Chips and cell libraries are designed such that the noise does not cross the specified noise immunity of the circuit.

It is exactly as you describe it: The logic circuit takes time $t$ to stabilize. This $t$ is given by the low-level description of the circuit (adding all the $t_{\text{high-low}}$ and $t_{\text{low-high}}$ in the longest path (the critical path). There are additional delays here, but I'll not discuss them here.)

Once we know this $t$, we can set the clock oscillation to be $\ge t$. That is, there will be a gap of at least $t$ time between one clock tick (which causes changes in the logic circuit), to the next clock tick (that samples the new output). By that second click, the outputs are already stable.

This second click now triggers a change in the inputs, which again changes the output: after time $t$, the output is stable again and another clock tick is allowed.

So the basic idea here is:

1. you first determine the time $t$ it takes the output to be stable
2. then you set the clock period to be larger than $t$.
• Yes, this much is clear. But what physically prevents the logic of the circuit to broadcast the noise in between the tick and tock? How do you enforce the sampling to coincide with the cycle of the clock? Oct 22, 2015 at 15:17
• To clarify.. The simple gate in my sketch may feed more circuitry downstream. What prevents it from feeding noise before the signal is "stable"? Is our ability to distinguish the signal from noise inherently linked to the fact that our perception "clock" is slower still than the system clock (otherwise we'd sample the noise before it stabilizes)? Oct 22, 2015 at 15:25
• @MaksimYegorov sorry, I don't understand your question. Flip-flops do two things on a clock: 1. they sample their input, and 2. they change the output accordingly. Each FF on a clock tick samples the output of the circuit before it and changes the input to the circuit after it. The time $t$ is the longest latency between two consecutive flip-flops. Sampling happens always after all the outputs have stabilized. If it is not the case, you lower the clock frequency until this happens in all FFs. Oct 22, 2015 at 15:38
• You can query the output of a flip-flop in between the tick tocks and get (possibly incorrect) output. There's a continuous (analog, existing at all times, possibly varying) signal propagated through the circuitry that is meaningful only if sampled on the clock. The question is, what mechanism enforces reading on the clock rather than in between? It appears that if our (human) attention span was shorter than (typical) system clock cycle, we'd be continuously sampling the noise? Oct 22, 2015 at 17:08
• Not to me. I sugget you look at Electrical Engineering. specifically, look for the tags "constraints", "delay", "clock-speed" there, and for the searching terms 'hold time' and 'setup time' and 'critical path'. Maybe asking in the Computer Science Chat (or the EE chat room) will be more convenient to communicate what exactly bothers you. Oct 22, 2015 at 18:17