I am currently reading the IEEE paper A Memory-Efficient Parallel String Matching Architecture for High-Speed Intrusion Detection by Kai Zheng, Bin Liu, Xin Zhang, and Yunhao Liu.

In the paper they propose a model for a memory-efficient multiple-character-approaching architecture consisting of multiple parallel DFAs.

I have read the paper and I have understood to an extent.

But when I think of implementation, could I simulate the SRAM, LE,BCAM etc.. as in the case of a network simulator (NS-2,OPNET,OMNET).enter image description here

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    $\begingroup$ Google: "Circuit simulator". There are plenty out there. Spice is an oldy but a goody. $\endgroup$ – Dave Clarke Oct 12 '12 at 6:51
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    $\begingroup$ Is the graphic taken from the paper? If so, please check it's license and credit it accordingly. $\endgroup$ – Raphael Oct 14 '12 at 9:23
  • $\begingroup$ Yes, one could using discrete event simulation which is what network simulators use. $\endgroup$ – Dan D. Oct 16 '12 at 6:36
  • $\begingroup$ Aside from implementation issues, I fail to see why it should not work. Without further information/insight, is this a constructive ontopic question? $\endgroup$ – Raphael Apr 8 '13 at 17:59

You can simulate the architecture using a hardware-description language.

Try VHDL (http://esd.cs.ucr.edu/labs/tutorial/) or Verilog ( http://www.asic-world.com/verilog/veritut.html) two of the most popular hardware description languages.


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