I am reading the book Computer Organization and Design. It compares instructions on memory and instructions on registers but doesn't say anything about the speed of instructions when the source operand(s) is/are constants. In that case which will be faster register operands or immediate(constant) operands ?
Like AProgrammer said, it depends on the processor.
We are in an age where there are many limiting factors based on physics in CPU construction. This means that distance traveled for an instruction and heat generated by a gate cause latency. In theory, this means that for a pipeline where the bottleneck is the decoding stage, this matters. With immediate operands, you would not need to travel to the register to grab the values, which is additional clock cycles and distance traveled. This would decrease latency, and thus increase speed.
However, in real world applications, this is very likely NOT the bottleneck, and so there will be little to no increase (if mandatory register access stages exist) in speed.
The relative performance of instructions using different operand types is somewhat dependent on the instruction set, the processor design, the code being executed, and even the execution environment.
With fixed length instructions (and constant operands that fit within the instruction format), there is no code size penalty for immediate operands and likely no decoding penalty, so even when the pipeline does not provide an advantage to using immediates the avoidance of using a temporary register and an extra load could give the use of immediate operands a performance advantage. (Even in this case, it is conceivable that instructions might be cached in a decoded format that causes code with many or larger immediates to be larger in the decoded cache than functionally identical code that did not "overuse" immediate data.)
The use of a temporary register (which could be avoided with load-and-operate instructions) increases register pressure, reducing the compiler's ability to retain values in registers. In a simple microarchitecture, such might also increase the register port pressure (a modestly more complex design would get the value by forwarding from the load operation and not from the register file) which might delay execution of other operations.
With out-of-order execution, an immediate operand is guaranteed to be available while a register operand would typically have to have its availability determined dynamically. This can be used to simplify the scheduling of operations. (A processor could predict that one operand will be the last available and so only have to check that operand's availability to speculatively decide the operation is ready for execution, later confirming availability of other operands and recovering from any wrong speculation.)
Immediate operands have the advantage of being implicitly prefetched via the instruction stream from reading cache block sized chunks from memory (i.e., immediates exploit spatial locality in the instruction stream). (In addition, accurate prefetching of the instruction stream is much easier than general data prefetching.)
The spatial packing of opcode and data can also be exploited by hardware; it is easier to read one 64-bit chunk than two independent 32-bit chunks.
In some cases the early availability of immediate operands in the pipeline can be exploited to improve performance. The most common example of such an optimization is the calculation of PC-relative addresses, which can be done before register read in the pipeline. A much less common example would be optimizing constant shift amounts; being able to "warm up" the shifter with the shift amount can reduce latency.
Immediate values also facilitate some predecode and trace cache optimizations. This is similar to how a compiler can perform some optimizations from knowing that a value is constant or within a certain range. The processor can use dynamic information unavailable to the compiler and estimate that fix-up costs would be less than the benefit from the operation. (Placing small values in the Register Alias Table is more convenient with immediates; the value will be known to be small and known when the RAT entry is normally written.)
Since a register operand is generally required anyway and some operations do not use immediates, pipelines are typically designed with limited exploitation of early immediate availability.
Aside from the obvious disadvantage of immediates being expensive to modify in most modern processors, immediates can also increase code size. The performance impact of greater code size is highly variable.
It is also worth noting that in some cases memory operands can be as fast or faster than register operands. This can be a consequence of port count constraints (where the cache ports provide extra means of sourcing operands) or specialized cache optimizations such as signature cache, stack cache, knapsack cache, etc.