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Has there been any research on the subject of applying information theory to a processors clock? It occurred to me that a clock is actually transmitting data that is used for synchronization of different processor components. Once I started to apply information theory concepts to the clock a lot of interesting ideas came up. I.e. clock speed is equivalent to bandwidth, the two voltage levels it transmits are the equivalent to symbols making is a 2-level transmitter (duh), and the logical limitations on how to usefully apply those two symbols is equivalent to noise. Processor manufacturers increase channel capacity by increasing processor speed and processor architects try to increase information rate by designing smarter encoding/decoding techniques like pipe-lining, branch prediction, speculative execution, and even multi-core processors.

After looking at it like this, and considering that systems designers are going to greater and greater lengths to squeeze greater information rates from just two symbols, wouldn't it make sense to increase the symbol rate? I don't mean going to ternary or quaternary or any other-ary processing, but just giving the clock more symbols or using multiple "clocks". Of course the incredibly high speeds in modern processors and the extremely tiny transistor sizes tend toward not doing so, but it does introduce some interesting thought experiments.

Has anyone explored this in an academic or experimental setting?

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    $\begingroup$ What extra information do you feel needs to be conveyed by the clock? It's just a synchronization signal: every X units of time, the clock tells all the transistors in the chip to update now. (OK, that's simplified by ignoring clock skew but it's the essence of the situation.) We don't want higher clock speeds so we can transmit more "information"; they're just to make the transistors update more often. $\endgroup$
    – David Richerby
    Feb 6, 2016 at 8:28
  • $\begingroup$ Of course, but consider even a simple pipelining scheme in a very simple "fetch-decode-execute" processor. You wish to get the next instruction fetched during say, the execute phase. This lets your next instruction finish one cycle earlier than it otherwise would have. The amount of circuitry necessary to accomplish this is pretty significant and complicated. I designed one once as an exercise. Actually, it just occurred to me that the phase generator does do what I was thinking of to some degree. It derives a second "clock" from the main one and that is used for more synchronization "data". $\endgroup$
    – Rory O'Hare
    Feb 6, 2016 at 8:46
  • $\begingroup$ "Processor manufacturers increase channel capacity by increasing processor speed and processor architects try to increase information rate by designing smarter encoding/decoding techniques like pipe-lining, branch prediction, speculative execution, and even multi-core processors". Do you have any references for this? I am curious myself. $\endgroup$
    – user56834
    Feb 9, 2020 at 5:54

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Technically, clock skew does this already. Specifically the technique known as "useful skew". When a data signal is going to travel from one storage element to another (both updating based on the clock), the clock that the source and destination elements receive are not quite the same.

In "useful skew", the clock at the destination is delayed such that the data has more time to travel before the capture clock edge arrives at the destination storage element. This allowed more distance of travel as well as more computation.

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