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I learnt in my computer architecture course on Caches, that if we keep the memory speed of a machine the same and half the clock cycle time, the miss penalty doubles. Why does this happen? What is logic behind it? I have emailed my lecturer but he has not replied. In a lecture he just explained if we change one thing then something else has to change to keep the system constant.

I don't know if this is specific to my course or not but this was written in one of the slides I saw:

lower CPI results in greater impact of stall cycles

I don't know if I should interpret this as a good thing or bad thing? Does it mean if we lower the cycles per instruction, that it will negatively affect the amount of stall cycles?

Similarly, I came across this question in an architecture book:

We are trying to reduce the execution time by 30% but this leads to an increase of 20% in the CPI. What clock rate should we have to get this time reduction?

Why would decreasing the execution time cause a rise in CPI?

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  • $\begingroup$ Assuming that main storage response time is constant, that is independent of the cache clock, you need twice as much clocks to wait during the penalty time. If penalty doubles this means that penalty is measured in clocks. $\endgroup$ – Valentin Tihomirov Mar 5 '16 at 20:59
  • $\begingroup$ I read my architecture book and I think this is more related to the law of diminishing returns and Amdahl's law. $\endgroup$ – Nubcake Mar 12 '16 at 0:46
  • $\begingroup$ More than what? Amdah's law says nothing about doubling the miss penalty. It says that if you increase your core speed (CPU with cache) more and more, the memory (cache misses) will more and more become the bottleneck and you won't gain much from improved core speed. $\endgroup$ – Valentin Tihomirov Mar 12 '16 at 7:40

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