I learnt in my computer architecture course on Caches, that if we keep the memory speed of a machine the same and half the clock cycle time, the miss penalty doubles. Why does this happen? What is logic behind it? I have emailed my lecturer but he has not replied. In a lecture he just explained if we change one thing then something else has to change to keep the system constant.
I don't know if this is specific to my course or not but this was written in one of the slides I saw:
lower CPI results in greater impact of stall cycles
I don't know if I should interpret this as a good thing or bad thing? Does it mean if we lower the cycles per instruction, that it will negatively affect the amount of stall cycles?
Similarly, I came across this question in an architecture book:
We are trying to reduce the execution time by 30% but this leads to an increase of 20% in the CPI. What clock rate should we have to get this time reduction?
Why would decreasing the execution time cause a rise in CPI?