I'm trying to create a FSM that multiplies a bitstream with a constant value (e.g 3).
I don't have a clue how to design such a FSM. Any hints?
I'm trying to create a FSM that multiplies a bitstream with a constant value (e.g 3).
I don't have a clue how to design such a FSM. Any hints?
Let $x_1 x_2 x_3 \cdots x_n$ denote the input string ($x_i$ is the $i$th bit of the input). Let $y_1 y_2 y_3 \cdots y_n y_{n+1} y_{n+2}$ denote the desired output string ($y_i$ is the $i$th bit of the output).
You want a finite-state transducer that, on input $x_1 \cdots x_n$, outputs $y_1 \cdots y_{n+2}$.
This is equivalent to asking for a deterministic finite-state machine (DFA) that accepts all strings of the form
$$x_1 y_1 x_2 y_2 x_3 y_3 \cdots x_{n-1} y_{n-1} x_n y_n E y_{n+1} E y_{n+2}$$
where $E$ is some special symbol that indicates "there's no more input" (end of the input).
There are lots of resources on how to design a deterministic finite-state automaton (DFA) that accepts a particular language. So, go use those resources to find a DFA that accepts that language. Once you've done that, you will be able to translate it back to a finite-state transducer as required.