# D - Latch or D Flip Flop?

I have a diagram (http://imgur.com/cET8Q14) where it is either a D Latch or D Flip Flop. I am trying to figure out which one it is and why. If it is a D Flip Flip, I also need to know which input is the clock. Can someone help me out ?

This feels like a homework question, but I'll at least try to point you in the right direction.

The difference between a latch and a flip-flop is that a flip-flop is clocked. At first glance, I thought it was a latch since there was no clock labelled as such, but this might not actually be the case. The clock is an input that will determine when the state of the flip-flop can change, so take a look at both of your inputs and figure out what will happen to the main RS latch (the two gates on the right) in each case. In particular, your A input catches my eye since it's directly tied to the two gates directly tied to your main RS latch.

Keeping these in mind may help:

NAND RS latch truth table:

D flip-flop excitation table:

$$\begin{matrix} Q & Q(t+1) & D \\ 0 & 0 & 0\\ 0 & 1 & 1\\ 1 & 0 & 0\\ 1 & 1 & 1 \end{matrix}$$

• o ok, thank you! I received A as clock and that it is a flip flop. Can you verify this? – Alex Park Apr 27 '16 at 18:44

A D flip-flop has a clock input (else it would not be a flip=flop) and a data input D. There are also gated D flip-flops which have a a gate input--the clock and data inputs are ignored unless the gate is enabled.