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I know that one of the techniques used by RISC machines to improve the pipeline is the delayed branch, but what other techniques do they employ, namely, can they use register renaming?

I know that Superscalar processors have register renaming, but a Superscalar processor can only be a CISC machine, right?

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    $\begingroup$ These terms : RISC vs. CISC, scalar vs. superscalar, delayed branches, register renaming, are orthogonal. Simple superscalar CPUs have no register renaming and can be RISCs (early examples : MIPS R5000, SuperSparc) $\endgroup$ – TEMLIB Jun 1 '16 at 23:48
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RISC machines can have register renaming, just like CISC machines can have register renaming. Register renaming is an aspect of the processor implementation, whereas RISC is an aspect of the instruction set, so they are fairly orthogonal: there can be two processors implementing the same architecture (i.e. accepting the same code), but in different ways (and with different performance characteristics), one with register renaming and one without.

The Wikipedia article gives the example of the Alpha 21264. Alpha is pretty strongly on the RISC side.

The Alpha 21264 is considered superscalar, by the way. I don't know why a superscalar processor would have to be CISC or RISC: again, the ability to process multiple instructions in parallel is orthogonal to the complexity of the instruction set. In fact, RISC processors are more likely to be able to parallelize instruction execution successfully, because the instructions are easier to analyze. But CISC processors can and do do it too.

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