I am trying to study for an exam and I noticed a lot of the questions follow the idea of "Changing the ISA". From my understanding the ISA dictates the structure and format of instructions, so changing instructions or the format (32 to 64 bit) would change the ISA. However I ran into a question which I am not sure how to answer.

"If we remove the branch delay slots, will the ISA be changed?"

My guess would be no, because we're not changing any instructions (right?), but I would like to get an answer from someone more knowledgeable.


2 Answers 2


The instructions set architecture (ISA) is the contract between the hardware designer and the software designer. Anything that changes the contract, changes the ISA.

The question you have to answer is: given every possible program written with this particular ISA, do any of them have different behavior (give a different answer) if we remove the branch delay slots.

  • $\begingroup$ Just to be sure I understood. Removing the branch delay slots might cause hazards, which in turn change the behaviour of the program, which means that the ISA has changed, right? $\endgroup$
    – Cristi
    Commented Jun 12, 2016 at 15:04
  • $\begingroup$ Another question (which I guess is a broader one - sorry for all this, trying to understand it better). From this wiki page: en.wikipedia.org/wiki/Instruction_set#Instruction_types Any change I would make to these things (data handling, memory ops, etc.) would result in me changing the ISA, right? Which also includes anything related to branching (Control flow operations on wiki page). $\endgroup$
    – Cristi
    Commented Jun 12, 2016 at 15:24
  • 1
    $\begingroup$ Depending on whether one includes this constraint in "with this particular ISA", one might want to write "given every possible timing-independent program". E.g., reading a cycle counter (and producing output with some dependency on that value) would invalidate the ISA test. (Performance counters present another exposure of microarchitecture/implementation and one that is not directly related to timing independence.) If one further limits "possible program"s to ones which do not use illegal encodings or expose 'unpredictable' output, then a non-hint extended ISA can be the earlier ISA. $\endgroup$
    – user4577
    Commented Jun 12, 2016 at 18:01
  • $\begingroup$ @PaulA.Clayton Could you explain what you said in a simpler way? $\endgroup$
    – Cristi
    Commented Jun 12, 2016 at 18:20
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    $\begingroup$ @Xzenon At the end of the day, removing branch delay slots does change the ISA not because of something so esoteric, but because it changes the meaning of the branch instruction from executing the next instruction unconditionally to only executing it if the branch condition is false. $\endgroup$
    – Random832
    Commented Jun 12, 2016 at 18:52

Branch delay slots (in those processor in the past that had them) meant that if one instruction did something that set condition flags, and the very next instruction in the branch delay slot did branch depending on condition flags, then it was guaranteed that the branch was taken or not taken according to the state of the conditions flags before the previous instruction.

Take the branch delay slot away, and now the branch is taken or not taken according to the state of the condition flags after the previous instruction.

The behaviour of identical code would be entirely different, therefore it's an ISA change.


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