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As I understand it, when we are on a virtual memory based system, we have to access memory 2 times (one for the Page Table and one for the physical address in RAM). But, how many times would we have to access if we had a TLB?

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Whenever you want to access some data item then its VA need to be converted into PA.Page table contains the required VA and PA mappings but it(page table) is stored itself in memory so you need 2 main memory accesses 1 for Page Table and one for actual Data.

TLB is faster type of memory than RAM.When there is a TLB hit you get desired Physical address in TLB and you have to access main memory once for actual data. But if there is a TLB miss, you have to access memory twice as in above case.

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Many systems use more than one level of page tables, so you may need to access memory more than two times.

With a TLB and assuming you have a cache hit, then you will only need to access memory once since TLBs are usually implemented in hardware. Otherwise, you will have to access memory the same amount of times you would if you didn't have a TLB (such as if the TLB is empty).

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