Of course, it depends on the type of CPU. Primitive 8 bits CPUs had no multiplier (until the MC6809 which had a 8bits x 8bits multiplier :-).
Modern CPUs have both fast integer and floating point multipliers. The FP multipliers are replicated for "multimedia" SIMD instructions and there are also plenty of fast multipliers in the GPU.
Depending on the transistor budget, one may make a pipelined 1 cycle throughput double precision (53x53 bits) multiplier, or make only single precision 1 cycle and 2 or 3 cycles for double precision. Some GPUs still have this sorts of limitations.
In a modern FPU, the multiplier is often coupled with an adder and the mul/add operation can be done in 3/4 cycles, pipelined (so that a result can be obtained every cycle, as long as there is no data dependency). The core multiplication part lasts 1 cycle, while the other cycles are used for data algnment, conversion, rounding... There are many tricks for implementing multipliers using fewer gates than cascaded adders. Look for Booth encoding, Wallace trees... but it is more about EE than CS.
x86 have some decimal parts, now obsoleted but still present.
There are the AAA, AAS, AAD, AAM instructions, unavailable in 64bits mode, wich are helpers for BCD arithmetics.
The FPU x87 instruction set has instructions to read/write decimal numbers from memory and convert on the fly to/from binary (internal registers are binary).
Some high end CPUs, notably IBM servers/mainframes, feature decimal FPUs specifically for financial operations with are officially based on decimal rounding and cannot be easily implemented exactly on binary FPUs.