I learnt that multi core processors have more than one processing units( i.e. the main executing units ALU etc.) and they are better at performance. I want to know how they share Physical memory. I'll take following example to make my question clearer - Say, There is a memory location M in physical memory and Two threads T1 and T2 running on different cores. Is it possible for T1 and T2 to access M at the same instance of time or do they have to wait for one other to complete access i.e. do they share the same memory bus so that they have to wait, for one another or Can they read M at same instance of time from two different memory buses? If former is the case, There is not much performance gain right, as they have to wait for memory bus to be free?

Summarising, Are memory operations independent of other cores or each core can only make a physical memory access when memory bus is free?

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    $\begingroup$ Is this a question about how abstract machines can deal with concurrency issues in a shared-memory setting, or is it about how i7 et al. actually do it? $\endgroup$
    – Raphael
    Sep 7 '16 at 14:26
  • $\begingroup$ The question is whether multi core systems' memory access happens in one after another way or they can access simultaneously i.e. at the same instance of time? $\endgroup$
    – AV94
    Sep 7 '16 at 14:32
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    $\begingroup$ Please re-read my question. Also, note that you are basically asking "how to deal with concurrency?" which is way too broad a question. $\endgroup$
    – Raphael
    Sep 7 '16 at 14:34
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    $\begingroup$ Check out "cache coherence". That's what you're looking for $\endgroup$
    – gardenhead
    Sep 7 '16 at 20:03

I learnt that multi core processors have more than one processing units

Well having more than one processing unit is something present even outside multi-code processors. Processors which are able to start the execution of several instructions in the same clock cycle are called super-scalar (the first super-scalar processor of Intel in the x86 family is the first Pentium).

Multi-core processors are in fact several processors on the same chip. (Sharing between cores is limited to cache, when sharing more you have architectures called with names like SMT -- simultaneous multi-threading -- or hyperthreading -- which is the name Intel is using).

I want to know how they share Physical memory.

Modern processors have usually cache (in the x86 family, that started again in the early 90's) so when a core need data, it is usually fetched from the cache without needing to access the main memory. There is several levels of cache. The lowest one being used only by a core. The other can be shared (and how depend on the details of a given model, for example you can have a four core processors with level 2 caches shared between 2 cores).

There is not much performance gain right, as they have to wait for memory bus to be free?

If one need to access the main memory, it's slow (my rule of thumb: level 1 cache access is 3-5 cycles, level 2 is 20-25 cycles, main memory is 100-150 cycles but again details may vary and I've not looked at them recently).


Memory access is not fully independent.

As long as the cores work on different memory ranges (with distance considerably larger than the size of a "cache line", which caches consecutive memory values), coordinating bus access would be the only problem... in theory.

In practice, cores (usually) have some local caching memory. This leads to two subproblems.

  1. If core A is writing to address X, the update might get stuck (for some time) in the local cache of A. Core B, using address X one moment later, might or might not get the updated value at X. A simple solution might be to write through, i.e. to commit write operations immediately to the RAM. Of course this will lead to degraded performance.
  2. Even if the processor is using write-through, core B already might have the contents of cell X in its local cache... this is, the outdated contents. Therefore, core B cache has to snoop on the address bus. Whenever there is write(!) access to a memory cell which is cached locally, core B has to mark the pertaining cache lines as "invalid". This is usually done at cache-line level, not on byte-level. This will further degrade performance.

Imagine to tell core A to write some bytes to all the odd, and core B to write to the even addresses in the same range. The accesses are disjunct, the result is well-defined, but performance will be dramatically worse than doing the same operation on a single core.

Cores perform best if operations involve local data (e.g. register operations), and, at large, memory accesses do not overlap.


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