This is related to an question asked and answered already, but I thought it was better to open a new question than necro a 1+ year old topic.

Below is a list of 32-bit memory address references, given as word addresses. 3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253

We want to optimize a cache design for the given references. There are three direct-mapped cache designs possible, all with a total of 8 words of data:

  • C1 has 1-word blocks

  • C2 has 2-word blocks

  • C3 has 4-word blocks.

In terms of miss rate, which cache design is the best? If the miss stall time is 25 cycles, and C1 has an access time of 2 cycles, C2 takes 3 cycles, and C3 takes 5 cycles, which is the best cache design?

I don't want the answer to the question, just want to clear some doubts about the concepts. This is what I think I know:

  • For C1: block offset is 0(1 word per block), index needs 3 bits for the 8 blocks, tag would be the remaining bits.

  • For C2: block offset is 1(2 words per block), index needs 2 bits for the 4 blocks, tag would be the remaining bits.

  • For C3: block offset is 2(4 words per block), index needs 1 bits for the 8 blocks, tag would be the remaining bits.

Is this correct? that part shouldn't be related at all with the access time, right? for example 180 = 1011 0100 in binary. So it would be:(tags would have a leading 0s)

C1: index: 100, tag 10110, no block bits

C2: index: 10, tag 10110, block 0

C3: index: 1, tag 10110, block 00

After determining those for every reference and cache design we find hit rate and we can answer first part.

For the last part we have to use that Total cycles =(hits * access time) + (misses * stall time) to see which is better. Correct?

Am I in the wrong on this? cause I saw different byte blocks on a book answer. Sorry for formatting issues or if i shouldn't have make a new question, completely new here.

  • $\begingroup$ I think you are right. I would do the same. It is a bit unfair to have exactly the same miss delay for C1 which only has to load 1 word and for C3 which needs 4 words. Due to the tag bits, C1 needs more memory cells than the other cache configurations. $\endgroup$
    – TEMLIB
    Sep 10 '16 at 21:32
  • $\begingroup$ @TEMLIB True, having same stall times doesn't really make sense. $\endgroup$ Sep 12 '16 at 17:29

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