Exactly how many clocks does a Computer consists of and how do they synchronize with each other?

Question

I am currently trying to understand how Computers are arranged and organized internally (so that I can learn Assembly Language) through an online book called The Art of Assembly by Randall Hyde. Irrespective of whether or not I'll learn Assembly, I'm finding it difficult to understand exactly how is everything synchronized in the Computer. I'm currently at 3.2 - System Timing topic.

Below are my observations and the things I currently understand not only from the book but also from the things I learned through understanding computers in general.

Reading the book, I've came to understand that there are atleast 2 clocks in the whole system. One is the System Clock which makes one of the lines within the Control Bus go HIGH and LOW periodically. The CPU also has it's own Internal Clock which controls the operations which are done by the CPU. Now the Internal Clock should be in sync with the System Clock for the whole system to make sense which means the control line (which oscillates between low and high) should be connected to the CPU so that both the clock combine and act like a single clock. But then this happened:

The above snippet is from the PDF version of the same book.

I still didn't get confused after reading this. I perfectly understood that the Internal Clock just runs twice as fast as the System Clock which is fine. My confusion came when the Author mentioned the words "On a 5 MHz 8088/8086 CPU the memory access time..." and "On a 50 MHz 80486, the memory access time...". The question is, 'How can CPUs have their clocks running at certain frequencies when their Clock depends on the System Clock?'. 'Shouldn't their Internal Clock run at a certain multiple of the System Clock?'. I've also came across overclocking the CPU and stuff. 'Won't that make the Internal Clock of the CPU go out of Sync with the System Clock?'

Perhaps the main problem in understanding how everything is synchronized in Computer is the understanding of the word 'synchronized'. And also, 'How many clocks are there in the Computer as a whole?'. Because "Zafaria Kansa" says on the following link on Quora that there are 'Internal' and 'External' Clocks on the CPU: https://www.quora.com/What-does-GHz-mean-How-does-it-relate-to-processor-speed (I don't have enough reputation to post more than two links). Does she mean 'System Clock' when she said 'External Clock'? How does everything fit together?

Answer 1

Modern processors tend to have more clocks than processors in the past, because that means when a part of the processor isn't used, it may be possible to switch off that part completely, including the clock, to save energy.

Clocks are often not synchronised, because synchronising and keeping them synchronised is expensive and complicated, and if you can make a part of the processor work correctly without synchronising its clock, that's overall cheaper.

Answer 2

The description is hopelessly outdated. For instance, "the Control Bus" ? I wouldn't even know what bus that would be. It's apparently not the "Internal Clock", so presumably "the Control Bus" is the external bus. Problem: modern CPU's don't have a single external bus. And it's not like each external bus has its own clock: modern high-speed parallel buses have a different clock per data line !

Yet another flawed assumption in your text there: that clock is in-band, not an extra pin. That would be too expensive, having one extra clock pin per data pin. Besides, that wouldn't work anyway. The reason to do clocking in-band is to eliminate the variation between pins.

As for the internal clock, a modern CPU may not even have a fixed number (!). Commonly, each core of a multi-core CPU can have its own clock, but an unneeded core may have its clock shut down to reduce energy consumption.

Of course, with those multiple cores, there has to be yet another bus to connect the cores on a CPU, and that too has a clock. This one can be especially funny: due to the limited speed of light, this clock can be both 0 and 1 at the same time, at different parts of the chip. Of course, half a clocktick later, it will be the other way around, so 1 and 0. The internal bus can have phase differences over its length.

You mention the 8086 and 80486. These are old chips. The increase in speed of modern CPU's is possible because of this added complexity. All those different clock domains prevent the fast parts from being slowed down by the rest of the system. Having 2 clocks, internal and external was just a first step, but today we can even use multiple clocks per bus.

Answer 3

If I am correct about your query then there are some of the links which I mentioned below that may help you to understand the procedure. But to make better understanding approach should not be how it is working the approach should be how it could possibly work.

Lets check with the first approach.

If you read some open documents of MCH you will see the PCI works on separate clock and FSB works on separate clock. Think of all the components working in the system works on different clock rate, the word synchronized doesnt mean that "If I say yes, at the same time you also say Yes", indeed it means things happenning at the rising edge of the clock. Now all the components such as circuits deal with busses like PCI, circuits deal with interrupt system and control unit itself has different clocks. One approach is in order to intercommunicate between the components the approach should be based on the handshaking signals. Lets suppose components X1 is the main component that deal with internal processing and component X2 is the component that deals with only ISA or I2C bus. Now data recieved by X2 should go to processing through X1, what handshaking signals required. The hypothetical approach is:-

1 X2 notification that he has the data to X1 2 X1 acknowledge and ask to share the data 3 X2 start sending the data by keeping another signal ON to tell the X1 that data is on the bus (Just like in RAM we have the concept of RAS and CAS signals) 4 Once the data is completed by X2 it sends complete signal 5. And X1 acknowledge

Second approach I read on the MP book for x86, based on my understanding.

There is separate clock generated circuit in the computer that sends the clock to the processor and to the system, This circuit is tunned by a variable for example 2Y is the clock frequency on which the computer processor work and processor and clock generator is designed in such a way that 2Y gives to the processor and processor is made aware that it receives the multiple of Y clock frequency like "2" in this case and the board designer (An important person) should know that Y is enough frequency for the operation of every component mentioned on the board, thats why when he send the board for selling in the Market he mentioned the list of specifications for the compatibility.

Third approach is my own idea where the system components have one controller and each controller has two clocks one that is running its part and the other for which it is communicating upstream with the single reference clock

Moreover if we study pentium structure there is one pin which is known as cache miss and also if you study X86 you will see one pin known as Data ready, such kind of implementation is done that if an environment comes where sync-synchronized (The idea of perfect matching) not be the option (Board designer person decision) then create the wait states until the data is reliably received.

Below are some links that might help you. Also search clock domain crossing protocols

https://en.wikipedia.org/wiki/Clock_synchronization http://paginas.fe.up.pt/~ee12248/Dissertation/wp-content/uploads/2015/03/PDI_ee12248.pdf