According to my lecture and wikipedia NOR and NAND flashes are the most common used. However there isn't really explained why people decided to use these logic gates instead of others. Can someone explain me, what are the factors deciding which gates to use and show how these gates match those properties best?

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    $\begingroup$ I can't answer this with respect to other circuits than NOR and NAND, but the difference between NOR and NAND is that Flash memory based on NOR circuits typically performs faster while those based on NAND circuits are more compact. Therefore, the NOR-type is used primarily for data and program storage because of faster access and the NAND-type for mass storage. (source). $\endgroup$
    – FK82
    Commented Sep 20, 2016 at 15:28

3 Answers 3


NAND and NOR are the only two binary gates that are functionally complete, which means that using just one gate type you can implement any circuit.

This greatly simplifies fabrication. As long as you can construct a single type of gate many times using the same technique, and can connect them arbitrarily, you can create any circuit.


The underlying reason is that digital circuits are not really digital.

A CMOS gate essentially looks like this:

Basic CMOS gate

The inputs are fed into two circuits: the pull-up circuit and the pull-down circuit. These two circuits are complementary, in the sense that the signal combinations which result in the pull-up circuit directing the "one" signal to the output is the exact opposite of the combinations which result in the pull-down circuit directing the "zero" signal to the output. Look up "CMOS circuit design" in your favourite search engine for more on this topic.

When designing a digital circuit, you want them to be as robust as possible. Each component should produce clean outputs no matter how degraded the inputs are. So, for example, in a 5 volt CMOS gate, it's typical to accept as "zero" any signal below 1.5V, and accept as "one" any signal above 3.5V, however the output signal should be less than 0.05V for "zero" and greater than 4.95V for "one".

Adhering to these rules means that the circuit can tolerate a certain amount of signal degradation. You can think of this as a hardware version of Postel's Law: be liberal in what you accept, and conservative in what you send.

Building non-inverting CMOS gates is just as easy as constructing inverting CMOS gates: you simply swap n-channel MOSFETs (hereafter referred to as nMOS) with p-channel MOSFETs (pMOS) and vice versa. And this would work if MOSFETs were perfect switches. However, they are not. Real MOSFETs transmit different signals with different quality due to how they are constructed.

I can't go into all the details here (this is an electronic engineering question), but the short version is that while nMOS transistors transmit a strong "zero" signal, they only transmit a weak "one" signal. Dually, pMOS transistors transmit a strong "one" signal and a weak "zero" signal. As a result, for the cleanest possible output, nMOS transistors are best used for pull-down circuitry and pMOS transistors are best used for pull-up circuitry.

This has the property that the gate is "fully restoring": the output signal is in a strong voltage range no matter what the input voltages were.

Non-inverting CMOS gates are non-restoring because the wrong type of transistor is used for each "pull" direction. The output signal is weak compared to a gate where you used the correct transistor type in each pull circuit. This means that the signal gets more degraded as you chain gates together.

(It is possible to design hybrid circuits, where you have a non-restoring gate followed by a restoring gate to clean up the output signal. You will often find this in non-monotonic gates such as XOR, for example. This is interesting stuff, but it's beyond the scope of this answer because it's not relevant to how flash memory works.)

It's a nice property that inverting gates are functionally complete (you can construct any circuit with them). In particular, you can just put an inverter stage on the output of any gate to get its non-inverting version. However, this is not why CMOS circuits are designed this way, and this is also not relevant to flash memory, which just has to be able to store and retrieve a bit. Inverting gates just behave better in real-world circuits.

Flash memory (and EEPROM memory, for that matter) is designed with a special kind of transistor, called a floating-gate MOSFET (or FGMOS for short). The details are unimportant, but regardless, the FGMOS transistors are still either n-channel type or p-channel type, so everything said above about which transistors should be used where still applies: flash memory cells are still, ultimately, inverting gates.

Now here's the speculation

We have officially reached the end of my knowledge of CMOS and flash memory. Now here's some stuff that I think may be true. I'd appreciate an expert opinion on this.

I believe that reading flash memory cells works on a principle closer to that of NMOS logic than CMOS logic, however NMOS gates are inverting for essentially the same reason that CMOS gates are.

I would imagine that while we want to think of a FGMOS as a switch, it probably behaves more like a non-ideal variable resistor in practice. So its "input" is probably already a little bit degraded. It may therefore be even more important to use a fully restoring gate to read its value in practice.


NAND and NOR gates are very simple to build in all the technologies that are currently being used. For example, NAND is a lot simpler to build than AND - if an AND is needed, then you realise that you can build NOT by putting the same value into both inputs of a NAND, and AND (x, y) is usually easiest implemented as NOT (NAND (x, y)).

Lucky enough, not only are NAND and NOR very simple to build, they also give you the advantages of orlp's answer. NAND and NOR are a bit more difficult for the human mind to grasp, but if you design computer chips, that's no problem.

And actually, NAND and NOR are each functionally complete, so you can build everything using only one type. And it depends on the technology which one is the one that is very easy to build. (If you need the other, then NAND (x, y) = NOT (NOR (NOT x, NOT y)).

  • $\begingroup$ Why is it simpler to build NAND than AND? both of them require just 2 transistors. and wouldn't it be simpler to build a not gate from one transistor rather than using a NAND gate with the two inputs equal to each other? $\endgroup$ Commented Jul 2, 2019 at 14:59

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