According to the lecture, a virtual address first goes to the TLB.
If the TLB hits, it is then checked, if something has to be either read or written from cache.
In case of writing, it is then checked, if the write access bit is on. If yes, then it is tried to write to the cache.
However now it can happen, that the Cache misses and this attempt is retried indicating that this could continue ad infinitum.
However now I wondered, if there can be really a case for this to happen.