According to the lecture, a virtual address first goes to the TLB.

If the TLB hits, it is then checked, if something has to be either read or written from cache.

In case of writing, it is then checked, if the write access bit is on. If yes, then it is tried to write to the cache.

However now it can happen, that the Cache misses and this attempt is retried indicating that this could continue ad infinitum.

However now I wondered, if there can be really a case for this to happen.

  • $\begingroup$ I don't follow you. Can you give a more specific scenario that you think would cause infinite retries? You are assuming an access to a virtual address A that is in the TLB, but what other assumptions are you making? $\endgroup$ – D.W. Sep 21 '16 at 19:34
  • $\begingroup$ Then the assumption of the lecture, the attempt is retried is not neccessarily true? I don't make any further assumptions, prob due a lack of information presented. I still research this topic. While doing so this (according to lecture) possible scenario came to mind. $\endgroup$ – Imago Sep 21 '16 at 19:35
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    $\begingroup$ If there is a cache miss during a write, either the write is propagated to main memory and/or other levels of caches (L2, L3...), or the cache line is loaded (read) before completing the write cycle : this is named "no allocate on write" versus "allocate on write". If the TLB indicates that writes are forbidden for the given address, a page fault (or a similar type of exception) is triggered and the write is never completed. $\endgroup$ – TEMLIB Sep 21 '16 at 20:27
  • $\begingroup$ @TEMLIB, write as an answer? $\endgroup$ – D.W. Sep 21 '16 at 20:45

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