So, I'm trying to do a computer architecture assignment and there's a question about dcaches. Here's the question:

Given a 16 word dcache initially filled with word address 0, 1, 2, …15 memory data (referenced by the datapath in that order). Below is the next sequence of data memory address references given as word addresses. 1, 18, 2, 3, 4, 20, 5, 21, 33, 34, 1, 4

a) Assuming the dcache is direct-mapped with one-word blocks, list if each reference is a hit or a miss. Show the state of the dcache after the last reference. What is the hit rate for this reference string?

I'm not asking for a solution but would just like to know what is considered a miss or hit and how this is calculated? Also, what would be the difference if the dcache had a two-word blocks instead of 1?

Any help is greatly appreciated.


what is considered a miss or hit and how this is calculated

A hit occurs if the request word is in the cache; if not, we have a cache miss.

It isn't clear how much you understand about hardware caches from the question, but I'll assume you at least know the definition of cache sets and lines.

In a direct-mapped cache, each cache set can hold only one line. Thus, the number of sets is equal to the number of cache lines. Usually, cache lines are many words long (e.g. 64-byte cache lines), but in your example a cache line consists of a single word. Since the cache can hold 16 words (lines), we can deduce that there are 16 cache sets.

Each memory address is mapped to a set. The set holding a memory address is determined by the address's set-index bits. If there are 16 sets, then each address must have $lg 16 = 4$ set-index bits. Let's assume these are the lower-order bits of the address. So, for example, address 7 will uses cache set 7 (because the binary representation of 7 is 00000111).

In this problem, the cache starts full (often referred to as a warm or hot cache). You are given a sequence of memory addresses. Each memory address will be either a hit or a miss, as defined earlier. If the address is a miss, the word at that address must be brought into the cache, and the old value is ejected from the cache.

Also, what would be the difference if the dcache had a two-word blocks instead of 1?

If the size of a cache line is two words, then you have twice as many values in your cache. It is then possible that a requested word is already in the cache, even if you have never requested that address before. This will happen if you previously addressed a word in the same cache-line as that word.

  • $\begingroup$ So, for the problem above, 1 is a miss, 18 is a miss, 2 is a hit, 3 is a hit, 4 is a hit, 20 is a miss and so on? $\endgroup$
    – El Dj
    Sep 26 '16 at 16:01

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