# Computer architecture pipelining

LOOP:LW    R1,0(R2)
SW    R1,0(R2)
SUB   R4,R3,R2
BNEZ  R4, LOOP


If we want to move an instruction into a branch delay slot what will be that instruction and the schedule of the instructions?

In the solution they have brought SW R1,0(R2) into the branch delay slot like this:

LOOP:LW    R1,0(R2)
SUB   R4,R3,R2
BNEZ  R4, LOOP
SW    R1,0(R2)


But according to me it will change the meaning of the program since R2 will be incremented by 4 before storing the word. Can anyone clear this?

• Welcome to Computer Science! The title you have chosen is not well suited to representing your question. Please take some time to improve it; we have collected some advice here. Thank you! – Raphael Oct 20 '16 at 9:20
• How will it change the meaning? – Raphael Oct 20 '16 at 9:21
• They are still teaching about branch delay slots? – gnasher729 Oct 21 '16 at 8:41
• Can you give more details about the question? I think the compiler should have scheduled SW R1,-4(R2) in the delay slot and not SW R1,0(R2) because that would lead to wrong results in the program. – Sai Gautham Nov 19 '16 at 8:13

Yes, moving an instruction must not change the meaning of the program. However, as you correctly identified, the sw instruction uses R2 which is later being incremented by 4. Thus unless the instruction is changed to sw R1, -4(R2) (as suggested by Sai), the altered program may perform differently.