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Have been trying to understand the image below which shows status of spinlock using cache coherence. Reference is Computer Architecture A Quantitative Approach------------------
Could anybody explain why there is a cache miss in step no.5 when P2 tries to execute swap.enter image description here

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In step 4 P2 tests the lock and sees the value is 0. But testing the lock is just a read operation, so P2 has the cache line in state shared. In step 5 P2 executes a swap operation, which is both a read and a write, so requires a coherence action (invalidate P1's shared copy) to acquire the cache line in state exclusive. It's a "cache miss" in the sense that the required state in the cache is incorrect, not in the sense that the data is missing.

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  • In step 2, there is a write invalidate (from P0) of the lock variable.
  • In step 3, P1 experiences a cache miss.
  • In step 4, P1 is waiting for the bus to become available.
  • Finally, in step 5, the bus becomes available and P1's request is satisfied.
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  • $\begingroup$ I understand, but what i am enquiring about here is-----why is P2 suffering a cache miss when it has the lock in it's cache in shared mode in step 5. $\endgroup$ – Abhishek Dhankar Nov 24 '16 at 4:02

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