# Spinlock using cache coherence

Have been trying to understand the image below which shows status of spinlock using cache coherence. Reference is Computer Architecture A Quantitative Approach------------------
Could anybody explain why there is a cache miss in step no.5 when P2 tries to execute swap.

In step 4 P2 tests the lock and sees the value is 0. But testing the lock is just a read operation, so P2 has the cache line in state shared. In step 5 P2 executes a swap operation, which is both a read and a write, so requires a coherence action (invalidate P1's shared copy) to acquire the cache line in state exclusive. It's a "cache miss" in the sense that the required state in the cache is incorrect, not in the sense that the data is missing.