I've been stuck on this for a while now, I've tried reading the related topics on cs.stackexchange as well as the textbook and youtube videos.

Suppose we have a 8KB direct-mapped data cache with 64-byte blocks.

Offset $= log_2(64) = 6$ bits

number of blocks $= 8k / 64 = 125$

$Index = 7$ bits

$Tag = 32 – 13 = 19$ bits

Then how do I tell whether or not I have a hit or a miss given an address?

enter image description here

Is it (Block address) modulo (Number of blocks in the cache)

Where block address = byte address / bytes per blocks?

For example if (block address) mod (number of blocks in cache) = 2, then does that mean row 2 of my picture is a hit?

  • 2
    $\begingroup$ Please do not use images as the main content. We have LaTeX available. $\endgroup$ – Evil Dec 9 '16 at 11:39
  • $\begingroup$ 8kB / 64 = 128. In addition to address bits, each tag has a Valid bit which is cleared at startup then set for each loaded block. Assuming an empty cache at the beginning, the 1st and 2nd accesses are misses, the third is a hit because the block "0100101" has already been loaded and the tags are equal. $\endgroup$ – TEMLIB Dec 10 '16 at 1:08

There might be multiple addresses which have the same index bits given a direct mapped cache. Once you have found the index for a address which is to be accessed you then need to compare the TAG field of the cache with the the TAG part of your address. If they match then you have got a cache hit otherwise it is a miss and you have some stall cycles.

  • $\begingroup$ DO I do that using the modulo operation? Then compare the mod, to the TAG part of the address? $\endgroup$ – okmanl Dec 9 '16 at 18:55
  • $\begingroup$ You find the index using the modulus operation on the address generated by the processor. The TAG bits of every address generated are unique. As in your example the TAG is of 16 bit. if the TAG bits of the address and the TAG bits in the cache match then it is a hit. if the TAG do not match it means some other address currently resides in the cache (Some other address which maps to the same index ). This is a miss and we then access the physical memory or L2 cache to bring the required address into our cache. $\endgroup$ – Shubham Singh rawat Dec 10 '16 at 4:04

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