You need to distinguish between how RAM is physically organised and how it is accessed, and how the instruction set of the computer allows accessing memory.
For example, on a modern Intel CPU, the instruction set allows reading and writing quantities of 1, 2, 4, 8, 16 or 32 bytes with byte addressing. For example, you could read 16 bytes starting at address 0x1005 according to the instruction set.
However, RAM is organised so that 32 bytes at a time will be transmitted between RAM and CPU, and those bytes must start at an address that is a multiple of 32 bytes. Therefore, the last five bits of the address are never used, and there are no address lines for those five bits.
In the example, the processor would read 32 bytes starting at address 0x1000 into a cache line and then provide the 16 bytes that the instruction wants from that cache line. If you tried to read 16 bytes starting at address 0x1015, then the first 11 bytes 0x1015 to 0x101f would be provided from that cache line, and then the next 32 bytes would be read starting at 0x1020 and 5 bytes provided from that cache line.
Different processors access different amounts of data at a time - a 1970's microprocessor one or two byte at a time, and things have increased since then. Different processors have different abilities to access larger items at unaligned addresses (at all, or at different speeds).