I am a little bit confused about how to calculate the memory capacity.

word=data lines size
byte=8 bit
n=adresse lines size

Most of the people use this formula to calculate the capacity of the memory: C=(2^n*word)/8 octet

Is this formula correct when speaking about byte-addressable? Because if we have byte-addressable memory, I think the capacity will be 2^n octet.

If this is correct why people use the formula in all cases? If not can you please explain why to me?

Thanks you.

  • $\begingroup$ It can depend on context, there is no absolute rule. Often, when the data bus size is larger than 8 bits, lower address bits don't exist, for example A[31:2] for a CPU with a 32bits data bus. $\endgroup$
    – Grabul
    Dec 26, 2016 at 17:03
  • $\begingroup$ Thanks you, but do you know why in most sources they use this formula to calculate the capacity? $\endgroup$ Dec 26, 2016 at 21:24
  • $\begingroup$ The sources are probably copying from each other, without caring about the meaning of the formula. You can tell that this is the case because they bother to give you a formula at all. $\endgroup$ Dec 27, 2016 at 8:38

2 Answers 2


This formula assumes that memory is word-addressable rather than byte-addressable. The number of words that can be addressed is $2^n$. If you want to convert this from words to bytes, you can use the formula (in which word stands for the word size in bits). If you want to convert it to kilobytes, for example, you need to multiply by the word size in bits, and divide by $8192$. And so on. Come up with your own formulas!


You need to distinguish between how RAM is physically organised and how it is accessed, and how the instruction set of the computer allows accessing memory.

For example, on a modern Intel CPU, the instruction set allows reading and writing quantities of 1, 2, 4, 8, 16 or 32 bytes with byte addressing. For example, you could read 16 bytes starting at address 0x1005 according to the instruction set.

However, RAM is organised so that 32 bytes at a time will be transmitted between RAM and CPU, and those bytes must start at an address that is a multiple of 32 bytes. Therefore, the last five bits of the address are never used, and there are no address lines for those five bits.

In the example, the processor would read 32 bytes starting at address 0x1000 into a cache line and then provide the 16 bytes that the instruction wants from that cache line. If you tried to read 16 bytes starting at address 0x1015, then the first 11 bytes 0x1015 to 0x101f would be provided from that cache line, and then the next 32 bytes would be read starting at 0x1020 and 5 bytes provided from that cache line.

Different processors access different amounts of data at a time - a 1970's microprocessor one or two byte at a time, and things have increased since then. Different processors have different abilities to access larger items at unaligned addresses (at all, or at different speeds).


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