If I had a single core with other cores that have access to a BUS the problem of transactional memory makes sense with the setting of the T bit and letting cores be able to see the caches of the other cores so they know if they're working on shared memory and they can therefore resolve the conflict.

The problem I'm having is understanding how this works in a hyperthreaded core. Does the core share the cache and split it into two? Does the cache line have 2 T bits instead of 1 to differentiate which "Core" is using which resource in the cache?

I have these guesses but can't find any definitive answers anywhere.

  • $\begingroup$ I don't think there is any official documentation of how Intel implements TSX, but providing extra tracking bits per cache line is the mechanism that makes the most sense (BTW, transactional memory tracks written and read and not just "used in transaction"). Partitioning the cache dynamically has issues (e.g., the two partitions would have to be kept coherent, requiring extra probing). $\endgroup$ – Paul A. Clayton Dec 26 '16 at 14:27
  • $\begingroup$ Yeah, that's what I was thinking would be the case. It's just annoying that there isn't a definitive answer out there. Sorry about the bad terminology, I'm still in the process of learning about it all properly. $\endgroup$ – Mulciber Dec 26 '16 at 15:36

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