If I had a single core with other cores that have access to a BUS the problem of transactional memory makes sense with the setting of the T bit and letting cores be able to see the caches of the other cores so they know if they're working on shared memory and they can therefore resolve the conflict.
The problem I'm having is understanding how this works in a hyperthreaded core. Does the core share the cache and split it into two? Does the cache line have 2 T bits instead of 1 to differentiate which "Core" is using which resource in the cache?
I have these guesses but can't find any definitive answers anywhere.