A per, from my understanding, instruction decode is a subcycle of Instruction fetch. Now say I have a three-word instruction to be fetched from memory(1 word opcode and remaining words operand address).
My doubt here is: will fetch cycle makes one memory reference and remaining instruction will be fetched in ID stage of Execute cycle or fetch itself fetches the complete 3 word instruction?
With this knowledge I am trying to answer the following question:
Consider a three word machine instruction
ADD A[R0], @B
The first operand (destination)
A[R0] uses indexed addressing mode with
R0 as the index register. The second operand (source)
@B uses indirect addressing mode.
A and B are memory addresses residing at the second and third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During the execution of
ADD instruction, the two operands are added and stored in the destination (first operand).
The number of memory cycles needed during the execution cycle of the instruction is:
3 Cycles 4 Cycles 5 Cycles 6 Cycles
The total cycle can be 4 or 6 depending on how many cycles fetch is taking. If fetch takes one then Execute will take 6; if fetches take 3 cycles(to fetch complete instruction) then execution will take 4 cycles.