# Fetching multi word instruction from memory

A per, from my understanding, instruction decode is a subcycle of Instruction fetch. Now say I have a three-word instruction to be fetched from memory(1 word opcode and remaining words operand address).

My doubt here is: will fetch cycle makes one memory reference and remaining instruction will be fetched in ID stage of Execute cycle or fetch itself fetches the complete 3 word instruction?

With this knowledge I am trying to answer the following question:

Consider a three word machine instruction

ADD A[R0], @B


The first operand (destination) A[R0] uses indexed addressing mode with R0 as the index register. The second operand (source) @B uses indirect addressing mode.

A and B are memory addresses residing at the second and third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During the execution of ADD instruction, the two operands are added and stored in the destination (first operand).

The number of memory cycles needed during the execution cycle of the instruction is:

3 Cycles
4 Cycles
5 Cycles
6 Cycles


The total cycle can be 4 or 6 depending on how many cycles fetch is taking. If fetch takes one then Execute will take 6; if fetches take 3 cycles(to fetch complete instruction) then execution will take 4 cycles.

The answer: It depends on the implementation in that particular processor architecture. If this is just a made up example of an architecture, it probably hasn't been thought through properly, so nobody knows the answer.

That said, if I had to implement instruction fetch, then it would fetch the whole instruction.

If an instruction is variable length then we fetch one word in fetch cycle then we decode that word and if it is more than one word then we fetch these remaining words in Execution cycle. Here fetch cycle takes one memory access always, irrespective of instruction length.

If an instruction is fixed length (say 2 words each instruction) then why to fetch only one word in fetch cycle, we fetch 2 words in fetch cycle, here fetch cycle takes 2 memory access as only one-word fetching at a time.

If nothing is given then we can't just assume variable length.

As @gnasher729 says, it is really case-dependent.

If your question is for the fundamental course purpose, it is better to figure out the specific implementation of processors (stimulators also) and instructions. There are some ways to analyze it generally, like the number of memory access, but not all instructions follow it either.