There are two aspects related to VIPT caches and aliasing. And the issues can be a bit different between instruction set architectures.
There are several ways to map the virtual addresses of each process to the external physical addresses.
Some use "process identifiers" or "address space identifiers" (iirc ARM, SPARC, MIPS) where each running process is given a different value used to select different page tables.
Some use "logical/physical" addresses where the addresses for each process (=logical) are translated o a larger address space (for example from 32 to 52 bits) (=virtual) shared between all processes, and TLBs transform these extended virtual addresses to physical addresses. PowerPCs are like that.
To avoid needing to flush all the TLBs and all the cache during each context switch, the cache tags (and TLBs) can store the corresponding address space identifiers or extended virtual addresses : Each adress of each process is different, and no aliasing is possible (well, sometimes aliasing is expected, for example where running privilegied kernel code mapped in the same virtual address range of all processes)
A more subtle issue is when several processes share the same physical memory area. This range of physical memory may be mapped in different virtual addresses by each process. Modification by one process may not be visible by the other. Particularly with write-back caches where writes are not immediately forwarded to RAM.
One solution, with the OS assistance, is to guarantee some alignment between processes depending on cache size, even if the virtual addresses are different between the different processes, they will be aliased in the same cache line, and will automatically eject one another.
Virtually Indexed caches are used principally on simple (old) CPUs, because of these aliasing issues. Nowadays, a very common technique is to limit each way of the L1 cache to the MMU page size (4kB or 8kB usually) so that the cache index is shared between physical and virtual addresses, cache fetch occurs at the same times as MMU address resolution.