In cycle stealing mode, is CPU idle during data transfer between peripheral devices or idle only for 1 cycle ( during shifting of bus controls ) ? Because I'm unable to understand these lines.
The DMA module is transferring characters at the rate of 1200 characters per second. or one every 833 microsecond. The DMA therefore steals every 833rd cycle.
Now, I think these lines make sense only if we assume CPU is blocked for 1 cycle not during 833microsecond(during DMA transfer). Please anyone help me where I'm wrong or am I missing something.