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In cycle stealing mode, is CPU idle during data transfer between peripheral devices or idle only for 1 cycle ( during shifting of bus controls ) ? Because I'm unable to understand these lines.

The DMA module is transferring characters at the rate of 1200 characters per second. or one every 833 microsecond. The DMA therefore steals every 833rd cycle.

Now, I think these lines make sense only if we assume CPU is blocked for 1 cycle not during 833microsecond(during DMA transfer). Please anyone help me where I'm wrong or am I missing something.

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    $\begingroup$ You are also assuming that the memory cycle time is one microsecond. That is really rather a long time by modern standards. A 4Mhz 8088 had a 1 microsecond cycle time, An 16MHz 80286 had a full speed cycle time of 0.125 microseconds and modern processors take way less time than that. $\endgroup$
    – Peter Camilleri
    Feb 1, 2017 at 0:28

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The CPU doesn't stay idle at all. It just gives the control of the data Bus to the DMA for 1 memory cycle . DMA transfers the data in this cycle which is consistent with it's transfer rate. Meanwhile the CPU can perform operations which do not involve the memory bus (by the means of cache memory and registers). In the scenario which you have presented assuming each instruction takes 1 cycle to complete , every 833rd instruction will have to wait for the DMA to complete its operation.

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  • $\begingroup$ One more thing, DMA is transferring 1 character per 833microsecond means It transfers a character (of whatever size) in 1 cycle time only, every 833microsec ? Right? $\endgroup$
    – Mr. Sigma.
    Jan 30, 2017 at 18:39
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    $\begingroup$ @user367180 yes we can safely assume the DMA transfers 1 character in one bus cycle of whatever size to the system memory. Also the DMA might be receiving data from some I/O system at a different speed which might be getting stored in a buffer if needed. $\endgroup$
    – Shubham Singh rawat
    Jan 31, 2017 at 5:24

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