Write-to-Read Relaxation means that for a processor:
later reads can bypass earlier writes
But what does that mean? What exactly is the difference between a read and a write for a Cache?
An example we had in the lectures about Processor Consistency:
Isn't c2 also a write for w? How can it be before c1? Why can CPU C execute c2 before c1?
Why does B see a1 before b2 while C sees b2 before a1?
Thanks in advance!