Write-to-Read Relaxation means that for a processor:

later reads can bypass earlier writes

But what does that mean? What exactly is the difference between a read and a write for a Cache?

An example we had in the lectures about Processor Consistency: Processor Consistency Example

Isn't c2 also a write for w? How can it be before c1? Why can CPU C execute c2 before c1?

Why does B see a1 before b2 while C sees b2 before a1?

Thanks in advance!

  • $\begingroup$ @TEMBLIB and why is c2 a read operation and not a write on w? $\endgroup$ – Seen Feb 4 '17 at 13:58
  • $\begingroup$ C2 is a read operation. Some out of order CPUs can rearrange reads, and if "*q" is from a secondary cache or from the cache of another CPU, it could be completed after C2. Depending on varying cache latencies, different CPUs may see a different order between accesses. Cache coherency mechanisms, atomic instructions and proper labelling of memory areas allows to build working multi-CPUs computers, but strong memory consistency can have some performance or complexity costs. (error submitting the comment, sorry !) $\endgroup$ – TEMLIB Feb 4 '17 at 13:59
  • $\begingroup$ U,V,W are registers, not memory locations (afaiu). $\endgroup$ – TEMLIB Feb 4 '17 at 14:01
  • $\begingroup$ Still, why is there a difference between e.g. v = *q and *q = 1? So write only refers to registers and read to cache? $\endgroup$ – Seen Feb 4 '17 at 14:06

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