Consider this example from Wikipedia:

P1 |    W(x)1   
P2 |        R(x)1   W(x)2       
P3 |                R(x)2   R(x)1
P4 |                R(x)1   R(x)2

Where P1 - P4 are different processors that issue read and write instructions to variable x in the given orders (their written and read values are given as well). It is clear that this example is Processor Consistent so it must also be Cache Coherent. But how is this possible in this example?

  • 2
    $\begingroup$ You are correct. It looks as though someone made an incorrect edit on the Wikipedia Processor Consistency page on Jan 16, 2017 that made the example incoherent. I undid the edit, so the example is no longer incoherent. (Although it is not obvious to me that the example is non-causal, so a different edit may still be required.) $\endgroup$ – Wandering Logic Feb 6 '17 at 14:17
  • $\begingroup$ Ok, but how can then an example look like that is not Sequential Consistent but Processor Consistent and still Cache Coherent? $\endgroup$ – tierriminator Feb 6 '17 at 14:29
  • $\begingroup$ Cache coherence means "for a single location there is a globally agreed sequential order." (I.e., all the processors see the reads and writes in the same order.) Consistency talks about the order of operations to two different locations. $\endgroup$ – Wandering Logic Feb 6 '17 at 14:34
  • $\begingroup$ So such an example would need to have reads and writes to at least two different memory locations, $x$ and $y$. $\endgroup$ – Wandering Logic Feb 6 '17 at 14:35
  • $\begingroup$ Ok, great, thanks, this cleared the confusion. $\endgroup$ – tierriminator Feb 6 '17 at 15:18

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