I am on studying a consistency model: weak consistency. weak consistency This model was first defined by Dubois et al. (1986), by saying that it has three properties:
- Accesses to synchronization variables are sequentially consistent.
- No access to a synchronization variable is allowed to be performed until all previous writes have completed everywhere.
- No data access (read or write) is allowed to be performed until all previous accesses to synchronization variables have been performed.
Here, S represents accessing synchronization variables.
But how is this possible ? I don't understand how can the event R(x)2 happens before R(x)1 of processor P3 while W(x) 1 happens before W(x)2 on processor P1.