Implement a one-bit ALU which takes two one-bit operands $a_0$, $b_0$, and produces a one-bit output $z_0$. The ALU has a two-bit control input $cont_0$, $cont_1$, with codes as shown below.

|$cont_0$|$cont_1$ |selects
|--- 0 ---|--- 0 ---| AND
|--- 0 ---|--- 1 ---| NOR
|--- 1 ---|--- 0 ---| OR
|--- 1 ---|--- 1 ---| XOR
(Sorry I didn't know how to make a properly formatted table)

The questions is:
Design the ALU using the smallest MUX possible.

I made a truth table as a start, then I came up with an ALU model, but I am not too confident with it. Any input on how to tackle this problem is appreciated.

Here's the truth table I made:
enter image description here

And here's the ALU that I'm doubtful about because it seems too easy of an approach.
enter image description here

  • $\begingroup$ You convert gates into 2X1 Mux, 4X1 into 2 2X1 Mux. $\endgroup$
    – Mr. Sigma.
    Feb 16 '17 at 6:49

If you consider the table as a 4 input combinational circuit and try to derive an expression from the K-map you will get $$Z_0 = cont_0'cont_1a_0'b_0'+cont_0a_0b_0'+cont_0 a_0'b_0+cont_1'a_0b_0$$

Now you can see the pattern with $a_0$ and $b_0$ so you can make a smaller circuit with a 4x1 MUX having $a_0$ and $b_0$ as selection bit.

  • $\begingroup$ How did you derive that equation? Wouldn't it be $Z_0 = cont_0'cont_1'a_0b_0+cont_0'cont_1a_0'b_0'+cont_0cont_1'a_0'b_0+cont_0cont_1'a_0b_0'+cont_0cont_1'a_0b_0+cont_0cont_1a_0'b_0+cont_0cont_1a_0b_0'$ $\endgroup$
    – Dragneel
    Feb 16 '17 at 7:18
  • $\begingroup$ You can simplify this expression and you will get the same result as given above. $\endgroup$
    – Deep Joshi
    Feb 16 '17 at 8:01

I am not entirely sure of all of the constraints on this question, but it seems to me that using explicit AND, OR, NOR, and XOR gates is kinda cheating.

The solution that ONLY uses a mux with no extra gates is a 16 to 1 mux. This would literally be based on the 16 element truth table listed in the question.

If a single inverter is allowed however, an 8 to 1 mux can serve.

c0 c1 a0   mux_channel  channel value
0  0  0         0          0
0  0  1         1          b0
0  1  0         2          not b0
0  1  1         3          0
1  0  0         4          b0
1  0  1         5          1
1  1  0         6          b0
1  1  1         7          not b0

BTW: This is an LU not an ALU as it does not perform any arithmetic operations.


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