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1M = 2^20, while the max number of memory locations for 16 bits is 2^16. How could there be a memory size of 1M x 16? Or can there? Wondering about this for a question we were given..

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  • $\begingroup$ Where do you get 1M x 16. Memory size is defined as number of addressable locations * size of one location. $\endgroup$ – Isu Feb 24 '17 at 17:04
  • $\begingroup$ Yes, you're right. 1M is number of addressable locations, and 16 is the size of one location. Question context: The first two bytes of a 1M X 16 main memory have .. But back to what I said, 16 bit word size is only 2^16 locations. $\endgroup$ – KenP Feb 24 '17 at 17:12
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It seems that a bunch of different things are being conflated here:

  1. Bits in an addressable memory location - 16 in this example.
  2. Addressable memory locations - 1M = 2^20 in this example.
  3. CPU word size

These can all be the same, or they can be entirely different. I will try to explain the differences:

1 - Bits in an addressable word. This can be ANYTHING. Typically this will be the same as the CPU word size - e.g., 32-bits for a 32-bit processor. However, it can be larger (e.g., direct access to a "double word") or smaller (e.g., individual byte access for a CPU that has a 16-bit or larger word size). On some CPUs there will be different instructions that use different size operands and addressing schemes - e.g., floating point instructions might work only on 32-bit ("single word") or 64-bit ("double word") memory locations but other instructions might work with individual bytes. In some designs, every byte can be addressed and accessed directly but 16-bit words only on even addresses (or 32-bit only on addresses divisible by 4).

2 - Addressable memory locations. Historically this was often double the addressable memory location size. For example, a typical 8-bit CPU such as the Z80 or 6502 could directly address 64k = 2^16 memory locations. However, there are quite a few variations. One significant one is a segmented memory addressing scheme such as that used by the 8086 family. This is one method of expanding the total addressable memory while keeping the addresses directly used by most instructions to a smaller size (16-bit in the case of the 8086). While there is some logic to keeping the address size (=# of addressable memory locations) the same as the CPU word size, in many (most?) CPU architectures that was simply not practical in many cases until we arrived at the era of affordable 64-bit CPUs.

3 - CPU word size. The CPU word size normally refers to the standard chunks of memory operated on and produced as results by individual CPU instructions. Another way of looking at it is the register size. However, there have been exceptions here as well. For example, the 8-bit 8080 has 7 8-bit registers and 2 16-bit registers (SP and PC - both needed to be 16-bit to match the memory address size) and some of the 8-bit registers could be used in pairs for operations that really operated on 16 bit values. Similarly, many 16-bit CPUs have some instructions that operate on 32-bit quantities either for floating point arithmetic or again for memory addressing.

Now that I've rambled on a bit (pun intended), back to the original question: 1M = 2^20, while the max number of memory locations for 16 bits is 2^16. How could there be a memory size of 1M x 16? A few possibilities come to mind:

  1. 16-bit CPU with memory locations 16-bits wide and a 20-bit segmented architecture like the 8086. (But not actually the 8086 as the 8086 address space was 1M x 8)
  2. 16-bit CPU with a 20-bit or larger (typically 31-bit or 32-bit) total word-addressable memory with the 1M being just a small portion of the potential addressable memory for that particular CPU.
  3. 16-bit CPU with 21-bit or larger (typically 31-bit or 32-bit) total byte-addressable memory with the 1M just being a small portion of the potential addressable memory for that particular CPU.
  4. 32-bit CPU with memory addressable in 16-bit words (i.e., 1/2 the native CPU word size) for better performance with instructions that don't need 32-bit words.

In case it isn't already clear, the CPU word size historically directly translated to the number of pins available for reading/writing memory. So an 8-bit CPU could interface with memory 8-bits at a time and a 16-bit CPU 16-bits at a time. That all changed famously with the 8088 which internally was a 16-bit CPU but externally only 8-bits. So while the 8086 could directly use 16-bit wide memory like the example 1M x 16, the 8088 could not. That difference gives the 8088 performance that is in some ways closer to an 8-bit CPU than a 16-bit CPU.

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Well, just consider the common 4Gx8 memory size. That's 4 billion octets. How's that possible? Simple: a unique address takes 4 octets. Now you can figure out how many 16-bit words you need for an address in your system.

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  • $\begingroup$ I kind of follow. 4G = 4 * 2^10 = 2^12 locations. If I am understanding correctly you are referring to a byte as an octet. Then, you say one address takes 4 bytes or octets which is 4*8=32 bits of memory. So, we therefore have 4G/2^5 which is (4 * 2^10) / (2^5) = 4 * 2^5 = 2^7 memory locations? (I don't think its supposed to be n-1 just worked out liked that so i must've messed up) $\endgroup$ – KenP Feb 24 '17 at 17:43
  • $\begingroup$ @KenP: 4G is 2^32 locations, not 2^12. (Kilo, Mega, Giga). And "octet" is unambiguous in discussions like this. $\endgroup$ – MSalters Feb 24 '17 at 17:46
  • $\begingroup$ sorry, messed my units up! Should've been 2^27 then. So your example is then still considered an 8 bit architecture, but we have 4G x 8 memory size where each individual memory location in the "4G" is 8 bits wide? And then we take 4 of those locations to create a single unique location for each memory address? Would this not be 32 bit architecture then? $\endgroup$ – KenP Feb 24 '17 at 18:02
  • $\begingroup$ @KenP: Not 2^27, as I said: 2^32 - indeed the common 32 bits architecture. 4Gx8. $\endgroup$ – MSalters Feb 24 '17 at 18:53
  • $\begingroup$ Thanks a lot. But this brings up another question - I thought word size was how we defined the architecture? This is not the case here if we're saying a 32 bit architecture has a word size of 8? $\endgroup$ – KenP Feb 24 '17 at 19:12
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You are looking at a memory chip here. 1M x 16 has $2^{20}$ addressable units, and each unit is 16 bits in size. Computers often use more than one memory chip. You could buy four such chips and combine them to get something that works as if you had a 1M x 64 chip. Or a 2M x 32 chip. Or a 4M x 16 chip.

The number of bits that a single memory chip stores in one addressable unit is completely unrelated to what the processor does. And "word size" is quite unrelated to the design of the memory chips. A typical modern computer transfers data between memory and processor one cache line (512 bits) at a time, not one word at a time.

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