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A 1-bit register:

1-bit register

Credit:
Elements of Computing Systems
by Noam Nisan and Shimon Schocken
ISBN-13: 978-0262640688

I know that the data flip flop outputs the input at the previous time step.

Based on this, I created this table (not sure if correct):

Note: For the Mux, 1 is for in and 0 is for DFF output.

$$ \begin{array}{|c|c|c|c|} \hline \text{In} & \text{DFF In} & \text{Load} & \text{Out} \\ \hline 1 & 1 & 1 & 0 \\ \hline 1 & 0 & 0 & 1 \\ \hline 1 & 1 & 0 & 0 \\ \hline \end{array} $$

The output is always alternating, no bit is being stored. It should constantly output 1 while load is 1 because that's what we initially stored.

I know that a register does actually store data, so something is wrong in my understanding of this.

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Your table is incorrect. A MUX element selects one of its inputs based on a secondary input. In this case it's a binary mux and load is used to select the input.

If we say that load = 0 means it selects the DFF and load = 1 means that it selects in you shall see that when load = 0 the circuit repeatedly refreshes the previous value, and load = 1 will read the new value from in.

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  • $\begingroup$ Surely this would make no difference to the output, the load column from top to bottom would just be inverted and read 1,0,0 $\endgroup$ – daka Apr 15 '17 at 22:04
  • $\begingroup$ @sudoman Consider the top row in your table. How can the output of the MUX be $0$ when both its inputs are $1$? I don't know your thought process behind the table so I don't know where the issue lies, but the table is simply incorrect. $\endgroup$ – orlp Apr 15 '17 at 22:10
  • $\begingroup$ Because the DFF outputs the previous input? right? and the previous input is nothing, so therefore 0 $\endgroup$ – daka Apr 15 '17 at 22:11
  • $\begingroup$ @sudoman You're confused about the MUX. The circuit can take an extra cycle to stabilize if DFF has a delay, but you misunderstand the MUX. While load = 1 the DFF does not feedback into itself. $\endgroup$ – orlp Apr 15 '17 at 22:15
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So I figured this out, the storage happens over the whole tock (high) of the master clock.

t -> t+ is the tick and t+ -> t+1 is the tock

Load and the bit we are trying to store must remain constant for at-least one whole tock.

So something like this:

$$ \begin{array}{|c|c|c|c|c|} \hline \text{Time} & \text{In} & \text{DFF In} & \text{Load} & \text{Out} \\ \hline 0+ & 1 & 1 & 1 & 0 \\ \hline 1 & 1 & 1 & 1 & 1 \\ \hline 1+ & 0 & 1 & 0 & 1 \\ \hline 2 & 0 & 1 & 0 & 1 \\ \hline \end{array} $$

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