I know the general basics of how RISC and CISC processors differ, but I also want to know whether the two differ in the way they handle interrupts.

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    $\begingroup$ I don't think interrupt handling has anything to do with the difference between RISC and CISC. That is, the involved design decisions are probably completely orthogonal. $\endgroup$ – Raphael Apr 16 '17 at 14:35
  • $\begingroup$ In a CISC processor, some instructions may run for a long time, so the hardware may decide to either cancel such an instruction, or to let it run to the end, or to save the state and be able to resume processing in the middle of an instruction after an interrupt. But then RISC sometimes had very complex instructions as well (load/store multiple words on PowerPC). $\endgroup$ – gnasher729 Apr 16 '17 at 19:21
  • $\begingroup$ Modern RISC CPUs have long-running instructions too (e.g. floating-point instructions, cache misses). As soon as you have out-of-order issue/completion or speculative execution, you need a mechanism to stop a stream of instructions when it's mid-execution. Interrupts are essentially the same thing. $\endgroup$ – Pseudonym May 10 '17 at 4:51

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