I'm currently studying computer architectures module, and during the workshop I came a across a series of questions that I struggled to being to answer.
The question goes;
*You have an L1 data cache, L2 cache, and main memory. The hit rates and hit times for each are: 50% hit rate, 2 cycle hit time to L1. 70% hit rate, 15 cycle hit time to L2. 100% hit rate, 200 cycle hit time to main memory.
What fraction of accesses are serviced from L2? From main memory?
My answer: (200*0.7)/15 = 9.3
To be completely honest, I don't know how to approach these type's of questions, I'd be grateful if someone could point me to resources.