I'm currently studying computer architectures module, and during the workshop I came a across a series of questions that I struggled to being to answer.

The question goes;

*You have an L1 data cache, L2 cache, and main memory. The hit rates and hit times for
each are:
50% hit rate, 2 cycle hit time to L1.
70% hit rate, 15 cycle hit time to L2.
100% hit rate, 200 cycle hit time to main memory.

What fraction of accesses are serviced from L2? From main memory?

My answer: (200*0.7)/15 = 9.3

To be completely honest, I don't know how to approach these type's of questions, I'd be grateful if someone could point me to resources.


The order of accesses is L1 → L2 (→ L3) → main memory. The chance of missing is $1 - p$ where $p$ is the hit chance.

In order for an access to hit L2 cache, it must have missed the L1 cache, and hit the L2 cache. So the chance is $(1 - 0.5) \cdot 0.7 = 0.35$.

In order for an access to hit main memory, it must have missed the L1 cache, missed L2 cache and hit main memory. So the chance is $(1 - 0.5)\cdot (1 - 0.7) \cdot 1 = 0.15$.

  • $\begingroup$ Oh, it's much simpler than I thought. Thank you! $\endgroup$
    – Vocaloidas
    May 1 '17 at 21:25

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