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If I have the sum-of-products expression B~CD + ACD how would I convert this so it could be implemented using 3-input NAND gates through DeMorgan's Law? Would this not generate the expression: ~(~(B~CD) ^ ~(ACD))?

It would seem I could implement this and use a 3-input NAND gate with 3-C inputs to act as a NOT gate but this seems wrong.

If this isn't the right place for such a question, let me know and direct me elsewhere if possible, I'll remove it.

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You have the basic rule that (a or b) = not (not a and not b), so you use that repeatedly. The first application gave you B~CD + ACD = NAND(~(B~CD), ~(ACD)). You're almost there:

NAND(~(B~CD), ~(ACD)) = NAND (NAND (B, ~C, D), NAND (A, C, D)) = NAND (NAND (B, NAND (C, C, C), D), NAND (A, C, D))

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