I am dealing with a standard MIPS architecture. If I have a branch instruction, for instance, beq, I know the results of the comparison in execute. However, the branching logic is actually in memory stage. Hence, doesn't that mean that I am technically losing 3 cycles(if the branch is taken) since the correct instruction is fetched during the writeback stage of the branch instruction? See the diagram below to see what I mean:
beq ... add ... add ... add ... ... label: sub C1 C2 C3 C4 C5 beq F D X M W add F D X add F D add F sub F
However, in this website: http://homepage.divms.uiowa.edu/~ghosh/2-14-06.pdf it says we only lose 2 cycles. This is because they are assuming as soon as you know the results of the computation (in execute), you can also fetch the correct instruction. I believe this is false since branching logic actually happens in MEM.
Where am I mistaken?