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Consider a three word machine instruction

ADD A[R0], @B

The first operand (destination) “A[R0]” uses indexed addressing mode with R0 as the index register. The second operand (source) “@B” uses indirect addressing mode. A and B are memory addresses residing at the second and third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand).

The number of memory cycles needed during the execution cycle of the instruction is:

a. 3 b. 4 c. 5 d. 6

My work till now:- As per my knowledge instruction execution has decode sub phase.So it will take 2 MR in decode phase to fetch the instruction.Then to read indexed addressing mode operand it will take one memory reference and since this is the destination also so in total it will have 2MR and then to read second operand it needs 2 MR. so in total i will go with 6 as the answer here. But i want to clear whether is it actual 6 or is it 4?4 because if we consider that decode phase is not part of the execution cycle.

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  • $\begingroup$ Could you explain 2 MR in "So it will take 2 MR in decode phase to fetch the instruction" $\endgroup$ – Isu May 26 '17 at 7:30
  • $\begingroup$ What i have learnt is that fetch always does 1 memory reference and then remaining words are fetched in decode phase of execution cycle.So given is a three word instruction.1 Memory reference can be done in fetch phase.and 2 memory reference will be done in decode phase to fetch remaining instruction.I hope i am clear. $\endgroup$ – rahul sharma May 26 '17 at 15:07
  • $\begingroup$ yes thanks, but I'm not sure if its the general case. $\endgroup$ – Isu May 26 '17 at 15:35

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