So I never really understood the von Neumann architecture, and have started to revise it as I wasn't in school during the lessons of the CPU. Can't really get help through my teacher as they wont respond to their email.
I have learnt about the von Neumann architecture, and now I need to know how the architecture differs from a contemporary processor.
I know that contemporary processors sometime use a mixture of Harvard and von Neumann architecture by using Harvard for the communication between the control unit and caches though for cost effective reasons von Neumann is used between the main memory and cpu.
The specification point wants to know how it differs though, and I will be very thankful for any responses that might answer the question.