RISC processors are pipelined, and have been since the beginning. That is, at a single time there are several instructions which are in different phase of execution. That mean that there is two different numbers that you can give for the execution time. One, the latency, which measures the time between the start of an instruction and its end. The other, the throughput, which measures how many instructions can be executed in a given time.
When someone says that RISC have single clock instructions, they are thinking about throughput, that is that RISC processors are able to execute one instruction per clock, and not latency, that is that it take one clock to execute any given instruction.
Early RISCs did not have multiplication instructions. That was more a consequence of manufacturing process limitation of the time, which would not have allowed to put a multiplier on the chip along with the rest of the processor, than a fundamental characteristic of RISC. With increased integration density, RISC acquired such instructions.
Note that it is possible to achieve bigger throughput than one instruction per cycle. For that, you need to be able to decode several instructions per cycle, and have several execution unit. That is something called super-scalar and high-end processors are super-scalar since the early 90's.
Note also that the possibility to achieve the theoretical throughput in practice depend on the program (you need to have instructions which are independent to be able to execute them in parallel, you need to have the data available, and thus have pattern of memory accesses and a memory sub-system which together allow to provide the data rapidly enough).