From the link below I understand the behaviour of different kinds of registers. However that raises few more queries in my mind.
What is behaviour of Regular registers when there are overlapping writes? Why do we study only MRSW regular registers? Do they behave like safe registers when there are overlapping writes? I mean, that the value read will be some legal value but may not be the one of the actually written ones.
For clarity need some sort of proof/illustration for the above. Since regular registers are said to be quiescently consistent even on overlapping writes we should have some value which was actually written by one of those writes.
In case of safe registers, if a read and write overlap the value read is any legal value that register could accommodate. So, is it also okay to conclude that we will see the same behaviour if there are multiple writes together?
I will also be thankful if you could point me to the tutorial with these questions covered.