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I read now several articles about RISC and CISC architecture. Most are rather exuberant enumerating all the differences between these architecture, but not necessarily why things are the way they are.

One point that struck out to me the most was about the RISC's feature of using hard wired parts in its processor and in particular so called "Random Logic" . According to wikipedia one might best view it as a "simple" decoder from "high level logic" to hardware features like AND and OR gates.

Unfortunately I didn't find more about "Random Logic", so I am a bit at a loss of its concept, design, purpose and why it is needed.

So I hope someone could go into more detail or simply provide references to read up on that topic online.

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  • $\begingroup$ The opposite of random logic is structured logic (e.g., ram arrays), which have regular placement and interconnect. This brief explanation might help. $\endgroup$ – Paul A. Clayton Aug 29 '17 at 1:31
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This all deals with one of the major, and complex tasks in any processor. Namely decoding instructions. On a simple conceptual level, this may be viewed as taking the contents of the instruction register and translating this into logic commands to the various functional units of the processor to perform the desired action and then fetch the next instruction into the instruction register and repeat.

Traditionally there are two competing camps called Random Logic and Microcode.

The random logic camp tends to look at the task as a sort of huge logic problem. Given an input (the instruction set), what outputs are needed (the instruction implementation). The result tends to look like a huge array of gates, flip-flops etc arranged in a non-intuitive (looking random, but no actual randomness here). Needless to say, for any non-trivial processor, this can be really complex.

The microcode camp on the other hand, maps each instruction to a stored program for a very simple but fast processor. Often, the microcode program is stored in very wide memory so that many program units can be simply connected to fields in the microcode with little or no additional decoding. In a sense, the microcode is implementing the random logic's output by table lookup.

These views are a gross simplification. Almost all random logic designs have small memory elements in them to simplify the state machines that are part of all processors, like the instruction fetch, operand decoding, or responding to interrupts. Likewise, almost all microcode machines employ some logic to speed up the decoding of the microcode to avoid needing insanely wide microcode memory. In addition, logic is often employed to allow the microcode to loop or branch to create more complex behaviour.

While microcode is extremely difficult to write, when an error is found, the code "simply" needs to be updated (assuming that you don't run out of microcode space, then well, problems) When a bug is found in the random logic decoder, it is not uncommon for the whole logic formulation to be affected. This can make random logic designs very hard to get right. The Z-8000 used random logic and its design was plagued by bugs in the instruction decoder. On the other hand, the simpler MC6809 also used random logic decoding and was highly successful.

The advantage of random logic is that it avoids the overhead of fetching the microcode from it's storage. In simpler processors avoiding this overhead can result in savings of silicon (that is money) and clock cycles (that is time).

RISC computers have much simpler instruction sets than CISC machines. This is a major reason why the random logic decoder is so often associated with RISC chips. CISC chips have intricate, complex instruction sets, so microcode is highly favoured for those designs.

I understand that most modern processors use a hybrid approach. Random logic for the simple and/or highly time critical stuff and microcode for the more complex behaviour and/or exception handling.

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