I've recently been studying MIPS as part of a CS course, but something bugs me. We've seen so far that MIPS increments the PC by 4 each cycle because each word is in fact comprised of 4 bytes (32 bits), each with their own address. I've also seen that a theoretical RISC machine has instructions that should only take a single cycle to execute.
Ignoring memory latency, how does it manage to generate an address for each 4 bytes? It can't have four adders for memory address calculation right? That'd be too expensive! Or am I incorrect in this assumption? I've also seen other architectures that manage to pull multiple bytes from memory (even multiple words) in a single step/cycle/instruction, but how is this achieved if each byte needs an address?