# How does MIPS ( or any other multi-byte word arch ) fetch a word?

I've recently been studying MIPS as part of a CS course, but something bugs me. We've seen so far that MIPS increments the PC by 4 each cycle because each word is in fact comprised of 4 bytes (32 bits), each with their own address. I've also seen that a theoretical RISC machine has instructions that should only take a single cycle to execute.

Ignoring memory latency, how does it manage to generate an address for each 4 bytes? It can't have four adders for memory address calculation right? That'd be too expensive! Or am I incorrect in this assumption? I've also seen other architectures that manage to pull multiple bytes from memory (even multiple words) in a single step/cycle/instruction, but how is this achieved if each byte needs an address?

• I don't know the details of MIPS but I don't really understand your question. First, why would four adders working in parallel be a problem? Second, why would you need them? Isn't the fetch instruction essentially "Get me the four bytes beginning at this address"? Why does that require computing four addresses? – David Richerby Aug 30 '17 at 17:07
• Imagine the following: You have the program counter at X, and would like to read four bytes. So you read the first byte at X, increment (to X+1) read that byte, increment (X+2), read that byte, increment (X+3) and read that byte and increment to X+4. Now the PC is incremented by four and you've read the next word of memory. Reading four NON-CONTIGUOUS bytes requires knowing four addresses, however reading the next four bytes in memory only requires one address (and knowing how many times to increment). – JustAnotherSoul Aug 30 '17 at 20:48
• @DavidRicherby I was under the impression that you absolutely need to be able to provide the 4 addresses in one step . JustAnotherSoul 's comment makes me realize that incrementing the PC 3 times in one clock cycle is also a possibility. Is a full adder required for incrementing the PC, or can a smaller circuit be designed assuming you only ever increment by 1 ? – coaxialgamer Aug 30 '17 at 21:04
• For all we know, memory is word-addressed, so the CPU sends to the memory controller the address of the first byte, and gets all 4 bytes in return. – Yuval Filmus Aug 31 '17 at 5:30
• It seems that the exact answer to this question depends on knowledge of the MIPS architecture, which is off-topic here. – Yuval Filmus Aug 31 '17 at 5:31

MIPS can load a 32-bit (4-byte) word in a single instruction (load word, LW). The fact that each byte of the word is individually addressable doesn't affect this. Effectively, the instruction says "Read the four bytes beginning at this address", not "Read the byte at this address. Increment the address by one. Read the byte at that address. Increment the address by one. Read the byte at that address. Increment the address by one. Read the byte at that address."

By way of an analogy, you can photocopy any two facing pages of a book simultaneously, even though each has its own number.

• And can someone explain to a theoretician like me why one would want bytes to be addressable? Why not just have addressable words? – Andrej Bauer Aug 30 '17 at 22:18
• @AndrejBauer As a fellow theoretician, I would guess it's because MIPS was designed in the 1980s, when memory was small and expensive. Many quantities (e.g., a character of text, back in the days before Unicode) fit in a single byte of memory and it would have seemed ridiculously profligate to use a 32-bit word to store an 8-bit value, and ridiculously inefficient to have to use multiple instructions to retrieve a whole word from memory and then shift and mask to obtain the desired byte. – David Richerby Aug 30 '17 at 22:31
• A theoretician might point out that at most 24 bits will be wasted on any string, not three times as many bits. Anyhow, yes those sound like plausible reasons. We're stuck with design decisions that made sense in the past. Programming languages are full of them. – Andrej Bauer Aug 30 '17 at 23:06
• @AndrejBauer See cs.stackexchange.com/questions/53936/… – Pseudonym Aug 31 '17 at 0:37
• @Pseudonym Caches, memory-mapped IO and anything else is massively over-complicating things for this question. The asker's difficulty appears to be that they believe that a memory can, for some fundamental reason, only return an 8-bit byte and that returning anything else (e.g., a 32-bit word) requires some special explanation, such as retrieving four bytes sequentially. – David Richerby Sep 1 '17 at 8:26

the cpu might have used an integrated circuit to clone one single instruction command to a number that the same number of instruction set executive commands,how for it will always be executed by transistors logic gate.Your question is unclear,i assume the command is a 8 bits so this 8 bits will be parsed and the output will have to be 11111111 and if not,it will be:
example: 10110010 so if the command is available,it will switch circuit to address 8th to send to a i/o another processing circuit to send the next commands to ram or peripheral devices.if not,it will switch to address 4th.

• Sorry, but I can't understand what you're trying to say, here. Also, MIPS instructions are 32 bits long (which is why the PC is incremented by 4 bytes). – David Richerby Aug 31 '17 at 7:30
• Maybe you could use more capitals and punctuations, it helps a lot to understand a post. Furthermore, if somebody says, "I don't understand X", it is very nice (and, from the view of the upvotes, very useful), if you take the advice and edit the post accordingly. For everybody getting the effort of commenting your post, there are a lot of others who didn't (and, some of them, may downvote the post). – peterh - Reinstate Monica Aug 31 '17 at 15:10