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Most of the learning material my knowledge of computers is based on revolves around early , byte addressable CISC-like machines , such as the SAP described in Paul Malvino's great "Digital computer Electronics" book. The concepts described fairly simple to handle to understand once you get the hang of it : the address of the instruction is taken from the pc to the MAR, the instruction is fetched from memory into the Instruction Register , and then the data is fetched . The rest of the machine cycle goes on .

Problem is , i've come to realize that more modern designs are far different in how they operate , and i feel that the concepts learned in that book are holding me back because they lock me into looking at everything from a byte-addressable view. When looking at SRAM such as https://www.alliancememory.com/wp-content/uploads/pdf/AS6C62256.pdf, it seems easy at first . The address of the byte is put onto the address pins as described by the datasheet .The chip select pin is asserted . The data is put on the input pins if necessary . The WE/OE pins are asserted depending on the operation . this made sense for me .

But recently , i've been learning about RISC , which seems to operate on fairly on fairly different principles with regard to the Fetch stage. I'd like to think i have basic pipe-lining concepts wrapped up.

I'm intrigued by how multiple bytes can be pulled off memory , because it clashes with my preconceived notions about how memory works . I used to think that only ONE byte and one byte only can be pulled off memory per instruction ( because only one address is specified by the PC ) , meaning that in order to increase instruction width , it would be necessary to have larger( word sized ) bytes . something like the memory chips linked above could be synched under a single address, with 32 bits being fetched off a single address . However , i've seen that this is not only inefficient , it's also not what is actually implemented. I've been told that yes , RISC machines do multiple bytes off memory in one cycle . A common explanation is the base address of the word is given , and somehow the 3 bytes after it are fetched as well . This is supposedly done using some magical hardware that is able to do this , but i've never been told how it is actually built and it's operating principles . As far as i've seen , memory has address lines , I/O , a chip select pin and a write/output enable pin . How does this [1] output 4 bytes at once ? I've sometimes been told that the cpu actually reads cache lines . But as far as i know , caches are just high speed SRAM that mirror part of main memory . I still can't understand it given my current understanding of memory . Where am i wrong ? can somebody help me out on this?

pin configuration

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    $\begingroup$ Again, why do you believe that there's something fundamental about memories returning a byte at a time? Why is reading eight bits at a time completely natural to you but reading 32 bits requires what you refer to as "magical hardware"? Really, what is the conceptual problem here? Why do you think that reading 32 bits at a time is at all different from reading 8 bits at a time? $\endgroup$ – David Richerby Sep 2 '17 at 21:50
  • $\begingroup$ because , as far as i can tell , those 32 bits require multiple addresses , that need to be fed to the memory decoder logic . I can't find a single mention of a way to get memory to get you the information contained in multiple locations , given a single location address. $\endgroup$ – coaxialgamer Sep 2 '17 at 22:09
  • $\begingroup$ "Give me the 32 bits starting from here." Why does it matter if the 9th-16 bits have their own address, too? $\endgroup$ – David Richerby Sep 2 '17 at 22:11
  • $\begingroup$ How is that achieved though ? How does the hardware understand that you're asking for the 32 bits starting at a given location ? I understand taking a high level approach of it , but when looking at data sheets for SRAM and DRAM , i don't see a single way how hardware can ask for the contents of multiple locations at once . An abstract example i was given was to think of each memory location as separate containers on a shelf , with each "container" number needing to be explicitly given by the instruction/PC . I just can't think of a way of doing it implicitly. $\endgroup$ – coaxialgamer Sep 2 '17 at 22:16
  • $\begingroup$ Update : Maybe SDRAM/EDO is the answer i'm looking for . Memory with a burst mode wouldn't need to be specifically called for each byte in a word . $\endgroup$ – coaxialgamer Sep 2 '17 at 22:24

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