Most of the learning material my knowledge of computers is based on revolves around early , byte addressable CISC-like machines , such as the SAP described in Paul Malvino's great "Digital computer Electronics" book. The concepts described fairly simple to handle to understand once you get the hang of it : the address of the instruction is taken from the pc to the MAR, the instruction is fetched from memory into the Instruction Register , and then the data is fetched . The rest of the machine cycle goes on .
Problem is , i've come to realize that more modern designs are far different in how they operate , and i feel that the concepts learned in that book are holding me back because they lock me into looking at everything from a byte-addressable view. When looking at SRAM such as https://www.alliancememory.com/wp-content/uploads/pdf/AS6C62256.pdf, it seems easy at first . The address of the byte is put onto the address pins as described by the datasheet .The chip select pin is asserted . The data is put on the input pins if necessary . The WE/OE pins are asserted depending on the operation . this made sense for me .
But recently , i've been learning about RISC , which seems to operate on fairly on fairly different principles with regard to the Fetch stage. I'd like to think i have basic pipe-lining concepts wrapped up.
I'm intrigued by how multiple bytes can be pulled off memory , because it clashes with my preconceived notions about how memory works . I used to think that only ONE byte and one byte only can be pulled off memory per instruction ( because only one address is specified by the PC ) , meaning that in order to increase instruction width , it would be necessary to have larger( word sized ) bytes . something like the memory chips linked above could be synched under a single address, with 32 bits being fetched off a single address . However , i've seen that this is not only inefficient , it's also not what is actually implemented. I've been told that yes , RISC machines do multiple bytes off memory in one cycle . A common explanation is the base address of the word is given , and somehow the 3 bytes after it are fetched as well . This is supposedly done using some magical hardware that is able to do this , but i've never been told how it is actually built and it's operating principles . As far as i've seen , memory has address lines , I/O , a chip select pin and a write/output enable pin . How does this  output 4 bytes at once ? I've sometimes been told that the cpu actually reads cache lines . But as far as i know , caches are just high speed SRAM that mirror part of main memory . I still can't understand it given my current understanding of memory . Where am i wrong ? can somebody help me out on this?