# Code size of Instruction set Architecture

For the following assume that values A, B, C, D, E, and F reside in memory. Also assume that instruction operation codes are represented in 8 bits, memory addresses are 64 bits, and register addresses are 6 bits, and data values are 32-bit integers (4 bytes each).

Output

Here are some calculation results

I don't understand Code size part, was not able to find it online too. Can someone explain how Code size part there is calculated? Thanks

• Unfortunately, made-up computer architectures are not standardized by their nature. Only your professor can tell you how instructed are encoded in your specific made-up architectures. – Yuval Filmus Sep 21 '17 at 13:15

Simply add up the number of bits per operation, register address, and memory address. I don't know why they mention data value, it doesn't really have any bearing on the calculation

In the stack code, there are three operations done on four memory addresses.

Stack size = 8 * operations + 64 * addresses = 8*4 + 64*3 = 224

In the accumulator code, there are three operations done on three memory addresses.

Accumulator size = 8 * operations + 64 * addresses + = 8*3 + 64*3 = 216

In the register-memory code, there are four register address accesses and three memory accesses

Register-memory size = 8 * operations + 64 * addresses + 6 * registers = 8*3 + 64*3 + 6*4 = 240

In the register-store code, there are six register address accesses and three memory accesses

Register-store size = 8 * operations + 64 * addresses + 6 * registers = 8*4 + 64*3 + 6*6 = 260