David Richerby's comment is right, in that the typical way it's "done" is to perform a subtraction and examine the "carry out" bit.
But I think it's worth stepping back for a moment and making a general comment about modern ALU design which may help you.
Thanks to Moore's Law, the number of transistors (and hence gates) required to implement a functional unit is not a serious limitation. Moreover, integer ALUs are not even close to the most power-hungry components of a modern CPU. So the main thing that needs to be conserved in a modern integer ALU design is propagation delay.
For essentially-single-cycle operations such as logic and add/subtract arithmetic, many modern integer ALUs are designed so that all potential operations are performed in parallel, and the "correct" one is selected with a multiplexer. This has the advantage that some of the multiplexer logic can be performed in parallel with the ALU operation, which again saves on propagation delay.
The same technique is used in floating point, incidentally. When performing a IEEE-754 floating point operation, the typical final step is that the result needs to be rounded correctly, using some logic which involves testing the answer and the FPU's current rounding mode. Many "real" FPUs essentially duplicate circuitry for some of the operation, performing three versions in parallel ("round up", "round down", and "pass through") and using a final multiplexer stage to decide which one to keep.
Of course, in real CPUs, ALUs typically aren't designed at the gate level these days, they are designed at the transistor level. So, for example, the multiplexer stage is probably achieved with high-impedance outputs followed by an amplifier stage to clean up the signal.